Input-output subsystem for digital data processing system

ABSTRACT

An input-output subsystem for the handling of data-transfer operations in a digital data processing system. The I/O subsystem provides a series of I/O controller-processors, designated as Line Control Processors, which are organized into groups to form a Base Module. A plurality of such Base Modules are organized to work with a main system interface unit called an Input-Output Translator which is part of the main host system comprising a processor and main memory. The Input-Output Translator (IOT) provides direct memory transfers to and from any connected Line Control Processor independently of the main processor. This arrangement simplifies the expansion of system capability for handling a greater number of peripheral devices on a simple economic basis while increasing data-transfer rates and reducing access errors in individual transfer operations.

This is a Continuation-In-Part of Ser. No. 728,457, filed Oct. 28, 1977which is entitled "Input-Output Subsystem for Digital Data ProcessingSystem".

TABLE OF CONTENTS Subject

Abstract of Disclosure

Cross Reference to Related Applications

Field of Invention

Background

Summary of Invention

Brief Description of Drawings

Description of Preferred Embodiment

Table I: Result Descriptor

Data Word: Table II

I/O Descriptor: Table III

System Description: General

Command Descriptor C/D

Descriptor Link

Descriptor Link: Table IV

Longitudinal Parity Word

Input/Output Translator: General

IOT - Initiation Module

IOT Descriptor Information Register

IOT - Connection Module: General; Poll Test

IOT - Data Transfer Module: General

IOT - Reconnection Module: General

Table V - I/O Descriptor - Data Field Address

IOT - Scratchpad Memory

Input Output Translator: Detailed Description

I - IOT - Glossary of Terms and Signals

II - IOT - Description of Hardware Elements

III - IOT - Description of Exemplary Operation

Descriptor Link

Addressing

Address Modification

Address Restore

Output Buffer Switching

Table Va - Switching Connections

Initiation Module Flow

Connection Module Flow

Data Transfer Module Flow

Reconnection Module Flow

Poll Request

Base Priority

Global Priority

IOT - Reconnection Sequence

Message Level Interface

Table VI: Message Level Lines

LCP Status Count - STC

Base Module - Backplane

Line Control Processor - General: LCP

Table VII - Status Counts

Poll Request

Distribution Card

Error Checking, Longitudinal Parity Checking

Line Control Processor: Detail

Descriptor Link in LCP

General: LCP - Peripheral Communication

Table VIII: LCP - Command Descriptors

Table IX: LCP Generated Result/ Descriptors

"State" Lines of Peripheral Device

Table X - State Lines

LCP - Peripheral Communication

LCP - Elements of

LCP - Peripheral Terminal Control

LCP - Data Flow Section

LCP - System Logic

LCP - Receipt of Instructions

LCP - Write Operation

LCP - Write Operation - Error Conditions

LCP - Read Operation

Table X - LCP Buffer - Address Locations

LCP - Read Operation: Error Conditions

LCP - Write Flip Read Operation

LCP - Echo Operation

LCP - Modes: Off-line and On-line

Table XII - LCP Operations - Summary

Table XIII - LCP - "Write" Command Descriptor

Table XIV - LCP - "Read" Command Descriptor

Table XV - LCP - "Write Flip Read" Command Descriptor

Table XVI - LCP - "Test" Command Descriptor

Table XVII - LCP - "Test Enable" Command Descriptor

Table XVIII - LCP - Conditional Cancel Command Descriptor

Table XIX - LCP - Echo Command Descriptor

CROSS REFERENCES TO RELATED APPLICATIONS

The following commonly assigned, and concurrently pending patentapplications are related to the subject matter of this application:

Ser. No. 728,456, filed Sept. 30, 1976, for Modular Block Unit forInput-Output Subsystem. This application was issued on Feb. 14, 1978 asU.S. Pat. No. 4,074,352.

Ser. No. 728,458, filed Sept. 30, 1976, for Intelligent I/O InterfaceControl Unit for I/O Subsystem.

Ser. No. 837,917 filed Sept. 29, 1977 (Continuation-in-Part of Ser. No.728,455, filed Sept. 30, 1976), for Interface System ProvidingInterfaces to Central Processing Unit and Modular Processor-Controllers.

Ser. No. 826,597, filed Aug. 22, 1977 for Modular Block Unit forInput-Output Subsystem (Divisional).

FIELD OF THE INVENTION

This invention relates to digital computing and/or data processingsystems and is concerned with the means and methods of controlling thetransfer of data between a variety of different peripheral devices andthe main memory of a central processing unit or main system. Basicallythe system involves taking the load off of the processing unit anddistributing it among a variety of Intelligent I/O Interface units whichcan work independently of the central processor in handling datatransfer operations.

This invention particularly concerns an input-output subsystem whereinmost of the main tasks of data transfer are relieved from operations inthe central processing unit and handled by a group of Base Module Unitseach of which may contain up to eight peripheral-controllers designatedas "Line Control Processors". Each of the Line Control Processor handlesthe specific requirements of a remote peripheral terminal unit. The I/Osubsystem further provides a distribution control means in each of theBase Module Units which controls and monitors communications andpriorities with respect to each of the Line Control Processors. The LineControl Processors provide an efficient arrangement which they canbuffer at least two full message block lengths of message data andpermit simultaneous data transfer operations to occur between the buffermemory within one of the Line Control Processors and a peripheral unit,and the data transfers between the buffer memory of another Line ControlProcessor and the Main Memory of the host main system. Provision is thusmade for a high data transfer rate in addition to the elimination ofaccess errors because of the quality and capacity of the data buffermemory for each peripheral and it means of interfacing the main system.

BACKGROUND OF THE INVENTION

The general configuration of a data processing system typicallycomprises a processor or processors, a main memory, and a plurality ofvarious types of peripheral devices or terminals (sometimes called I/Ounits), which more specifically may be card readers, magnetic tapeunits, card punches, printers, disk files, supervisory terminals, and soon. The optimum systems generally involve the configuration wherein theperipheral devices are handled by independent interface control units sothat the processor is free to access and process data contained in themain memory. In configurations having separate control means for theperipheral input-output devices, it is possible to have parallel orconcurrent processing occurring at the same time that input-output (I/O)operations occur. These concurrent processing I/O operations occurwithin the same program which operates through one of the processors,and which also initiates all input-output operations. In addition theprogram must have some means of determining when the I/O operations areinactive or have been completed.

As an example, if a program calls for a file of data to be loaded intothe main memory, it must be able to determine when that operation hasbeen completed before it can go ahead to make use of the data. Thus, aninput-output operation is initiated or started by the program, as bysome type of "initiate instruction" which provides, typically, anaddress pointing to an "I/O descriptor" which is stored in the mainmemory. This descriptor identifies the peripheral device from which datais to be received and/or transmitted, it identifies the type ofoperation such as a "Read" or a "Write", and also identifies the fieldof main memory locations to be used in the input-output operation.Generally this I/O descriptor is transferred to a control means (I/Ocontrol means) to control the transfer of data between the peripheralterminal device and the main memory.

When the input-output operation is "complete", such as by the transferof the data from the peripheral unit to the main memory to load the mainmemory, then there is a need for some type of a completion statement,which is typically referred to as a "Result Descriptor". Usually this istransferred from the I/O control means to some specific location in mainmemory known to the program being used. Typically, the Result Descriptorincludes information identifying the particular peripheral terminaldevice and further includes information as to the result of or thestatus of that particular input-output operation, -- thus, to provideinformation as to whether the transfer was complete and correct, orwhether any exception conditions occurred or whether any errors occurredor any other peculiar situations arose in regard to the transactioninvolving that particular peripheral terminal device.

Thus, when a program initiates an input-output operation, the programmust have some means to determine when the input-output operation hasbeen completed. A standard technique in this respect is for the programto have instructions to interrogate the Result Descriptors periodically,to determine when and if a particular input-output operation has beencompleted. However, it is much simpler if the input-output control meansindicates when the transfer operation is finished. In accomplishingthis, it is usually necessary to interrupt whatever operation theprocessor has underway, and force it to examine the Result Descriptorsand to take appropriate action. This stopping or interruption of theprocessor's activities is generally designated as an "Interrupt".

Thus, when an interrupt occurs, the processor must stop the program itis working on, it must make a fixed notation of what point in theprogram execution it was interrupted and it must then store the contentsof certain registers and control flip-flops so it can have informationas to where it should return in the program after the completion of theinterrupt cycle; and then the processor must transfer its attention andoperation to the program designed to handle and service the Interruptcondition.

Certain systems such as the system described herein, have a program forservicing "Interrupt" conditions, which program is sometimes referred toas MCP or a master control program. This program must keep a record ofcurrent input-output operations and associate the particular Interruptwith the particular input-output operation that caused it. Then it mustanalyze the results of this Interrupt cycle to see if any unusualcircumstances or exceptions occurred or if an error condition wasreported, so that corrective and appropriate action may be taken. TheInterrupt program must take the results of the input-output operationand make them available to the program that initiated the input-outputoperation and then further determine if other input-output operationsare waiting to be initiated and, if so, to take action to initiate otherneedful input-output operations. Such an MCP is discussed in U.S. Pat.No. 3,693,161.

In many of the prior and present system configurations, many calls orrequest for memory access would come in to get memory service, butbecause of the limited bandpass and time available for variousperipheral units, many I/O transfers would be incomplete and cause"access errors".

Also many of the prior art system configurations provided only one ortwo communication paths or channels to a multitude number of peripheralterminal units so that I/O transfer of a particular peripheral terminalunit had to wait their turn in sharing access and use of acommunications bus. This introduced congestion and delay into thesystem. It also made difficulties in systems involving multi-programmingsince efforts are made to match a job having heavy input-outputrequirements with another job that is "processor-bound" and which hasonly limited input-output requirements.

Many of the present day data processing systems have a singlecommunication path or a limited number of communication paths betweenthe central processing unit and the peripheral units. Generally withinthe communication path there is one or more "input-output control"means. When an input-output path is requested by a processor, the pathwill only generally become available when: the peripheral unit is notinitiating a transfer operation; the peripheral unit is not busy in atransfer or other operation with the input-output control means; theperipheral units or its input-output control means is not busy withother operations.

The data-transfer rate of the input-output control means is, of course,a limiting factor in the operation of the system since the often slowtransfer rate of certain peripheral units (which are passed through theinput-output control means) will unnecessarily tie up the processor andmemory activity to the low speed of the peripheral terminal unit.

Thus, many data processing systems have come to be provided with aplurality of input-output control means which include buffers, to permita particular peripheral or group of peripherals to communicate with themain system. When there are a plurality of input-output control means(through which pass the communication channels to individual peripheralunits or groups of such units) some prior art systems have used themethod of operating the data transfer operation in a sequential fashionso that the various input-output control means take turns in serving theperipherals which are associated with them.

A difficulty arises here in that certain peripheral units and theirassociated input-output control means are busier than others, andcertain of the channels involved actuatlly need more communications-timethan they are getting. A "channel" may be looked at as a communicationpath between the main system, through the input-output control means,over to the peripheral unit. Thus, there can occur situations wherecertain channels are "short changed" to the extent that a great numberof "access errors" will be developed. Access errors involve thesituation where the data bytes being transferred through theinput-output control means do not comprise complete message units butconsist only of non-usable fractions of message units. As a result ofthis, the central processing unit would not be getting or transferringuseful information and would have to become fixated on continuallyrequesting the same input-output operations over and over again. Thus,when the peripheral units are placed in a situation where they areunable to send or receive an entire message unit or record, then thelikelihood of access errors occurs which leads to uncompleted cycles inregard to a particular channel and no successful completion of transferof the required information data.

It is desired that the maximum transfer of data occur through thementioned plurality of input-output control means, and without suchaccess errors which lead to incomplete cycles of data transfer (whichare unusable, and the time period of which is wasted and of no use, thustying up valuable processor time).

Thus, in such a system configuration, problems arise in regard to howmuch time should be allocated to each of the individual channels fordata transfer operations and the further problem of which channelsshould be given priority status over the other channels.

Now, in data processing systems where multitudes of peripheral units areinvolved (many of which are at differently located installation sites)it is necessary to have groupings of input-output control means tohandle the variety of peripheral units at each given site. Thus, thepriority problems involve not only the priority to be given as to thecompletion among peripheral units at one local given site, but alsoinvolve the priority problems of priority allocation as between thedifferent locational sites, each of which have their own input-outputcontrol means.

SUMMARY OF THE INVENTION

The present invention involves a digital data processing system for thecontrol and handling of input-output operations (data transfers) asbetween a plurality of various types of peripheral units and a centralMain System (Processor and Main Memory).

The present invention describes an I/O subsystem which uses a series ofI/O processors (LCP's) each of which executes instructions involvingdata transfers between a specific peripheral unit and a central mainsystem (processor and main memory). Two types of I/O subsystems may beprovided, as discussed later, however, the Line Control Processors areused only in the second type of I/O Subsystem described hereinafter.

One I/O Subsystem is a system wherein a type of intelligent interfacecontrol unit, designated as a "Line Control Processor" (LCP), is used,and wherein each LCP, while performing the same basic functions, isspecifically oriented to control and handle data transfers to and from aspecific type of peripheral terminal unit. For example, a basic LCPwould be adapted for each specific instance to handle a card reader, adisk unit, a train printer, or other special type of peripheral unit.The LCP's are placed in groups, typically, of eight units, to form anLCP Base Module. Then each of the Base Modules are grouped in a set ofthree to form a LCP Cabinet Unit. A plurality of such LCP Cabinet Unitsmay be used to constitute the first I/O Subsystem.

Another I/O Subsystem is provided for those types of peripheral terminalunits for which no specific Line Control Processors (LCPs) have beendeveloped. This second I/O Subsystem is organized so that a CentralControl unit is provided to control the pathing from the CentralProcessor and Main Memory to selected input-output channels whichprovide a data path to individual peripheral units. These individualchannels will each have their own memory buffer and connect through theCentral Control unit over to the Main System.

The I/O subsystem using the Central Control is merely describedsupplementarily herein and is not part of the features of the LineControl Processor which is part of another type of subsystem.

In the I/O Subsystem using the Line Control Processors, the Main System(of Processor and Main Memory) is also provided with a unit called anInput-Output Translator unit (IOT) which becomes part of the Main Systemand provides an interface between the Main System and anotherdistribution-control interface designated as "Distribution Card Unit"which handles a Base Module, (a group of Line Control Processors) andwhich connects a selected individual Line Control Processor into the LCPI/O Subsystem.

The Line Control Processor's (LCP's) are organized in groups of eightcalled the LCP Base Module each of which has a single "Distribution CardUnit" which provides the interface between the Input-Output Translator,IOT, of the Main System and the eight LCP's of any given Base Module.Each Base Module also carries a Maintenance Card unit which can provideall maintenance and checking functions for the group of eight LCP's ofthe Base Module. Each Base Module is also provided with one common"termination Card Unit" which provides common clocking functions for allthe LCP's of the group and also provides proper terminations for thetransmission lines which connect the various LCP's, the DistributionCard, and the Maintenance Card of that particular Base Module.

The IOT of the Main System works in a unique relationship with theDistribution Card Unit of the Base Module of the LCP's in the LCP I/OSubsystem, serving to setup data-transfers between the peripheral unitsand the Main Memory in a fashion that does not burden the CentralProcessor and which permits concurrent data-transfer operations to occurbetween any number of peripheral units and the Main Memory. This isfacilitated by the use of a record-length buffer memory in each LCP. Thedata-transfer cycle is accomplished using complete data message-blockswhich thus prevent "access errors" from occurring.

The embodiment of the invention described herein provides a system whichhelps alleviate certain problems inherent in prior art systems. Byproviding a separate channel from the Main System to each peripheralunit, there is no need for data transfers (between a particularperipheral unit and the Main System) to have to wait for the use of ashared communication channel, since each individual peripheral unit isprovided with its own channel, and thus each of the plurality ofperipheral units can simultaneously and concurrently consummate inputoperations without any further requirements from the processor orwithout interference to processor operations. The input-outputdata-transfer control means in the subsystem is provided by anindividual "Line Control Processor" (LCP) for each peripheral unit. The"Line Control Processors" accept input-output commands from the MainMemory (via the I/O Translator unit) and they execute these commandsindepdendently of the main processor, so that input-output controloperations are performed in parallel with and asynchronously withprocessing.

A memory control unit 10_(c), FIG. 1A, regulates the flow of databetween the Main Memory, the Central Processor and the I/O Subsystem. Itallows each of the system components to have access to Main Memory on apriority basis, giving the highest priority to the I/O Subsystem. Sincethe Memory control operates independently of the Processor, theProcessor is free to perform memory-independent functions at the sametime that memory accesses are being granted to the I/O Subsystem.

The Line Control Processors are each provided with memory buffers whichcan store an entire message-block or record-length of data. Thus, datatransfers between Main Memory and the Line Controller Processor can takeplace at high speed and constitute a complete message-block in itself.Since a complete message-block of data is transferred in any givencycle, the problem of access errors is eliminated so that no furthermemory cycle time is required to complete "incomplete former datatransfer cycles", which might occur absent the record-length buffer.

The Line Control Processors are functionally the same except that minorvariations may occur so that they are adaptable to work with differenttypes of peripheral terminal units, and, as such, the LCP's are"transparent" to the Main System.

In certain cases, there are peripheral units and data storage devicesinvolved for which no specific Line Control Processors have beendeveloped. In this case, there is used another input-output controlsubsystem (using Central Control units as described in U.S. Pat. No.3,512,133) which can operate in parallel with the LCP I/O Subsystem andits Line Control Processors (LCP).

The main or central system of the described embodiment, which mayinclude the Processor, the Main Memory, and the Memory Control, isfurnished with a unit called an Input-Output Translator or IOT. The IOTis a special portion of the Processor which, upon receipt of an I/Odescriptor from memory, works in conjunction with the LCP Base Module toestablish connection to the particular LCP in the channel specified bythe "Initiate I/O" instruction from the program. The IOT translates theI/O descriptor into a form (Command Descriptor) recognizable to the LCP(Line Control Processor), and when connection is established, passes thetranslated descriptor over to the LCP after which the data transmissionmay begin. During the time that data is being transferred between LCPand the Main System, the IOT, upon demand by the LCP, requests memoryaccesses, addresses memory, then modifies and compares the dataaddresses. The IOT controls the routing of data between the selected LCPand the Main System, and it performs translation (ASCII/EBCDIC) of thedata if so required. ASCII/EBCDIC refers to American Standard Code forInformation Interchange/Extended Binary Coded Decimal Interchange Code.Upon completion of an operation, the IOT accepts Result Descriptor (R/D)information from an LCP and then stores the Result Descriptor (R/D) in apredetermined location.

The Line Control Processor, (LCP), is a device which upon receipt of aCommand Descriptor (C/D) from the Main System, via the IOT, establishesa communication path to a selected peripheral unit. Once this path isestablished, the LCP accepts data from or passes data to, the peripheraldevice. Since each LCP has a "data buffer" (typically 256 words), thendata can be transferred to and from the peripheral device at thecomparatively low speed rate of the peripheral device; then, when thebuffer is full, the data can be transferred to the central Main Systemat the highest rate permitted by speed of the Main Memory. Thus, aunique interworking relationship exists between the IOT (Input-OutputTranslator) of the Main System and the LCP, which is the interfacecontrol between the peripheral units and the Main System. Further, aunique working relationship exists between each LCP and the DistributionCard Unit of its Base Module, which interfaces a given LCP to the IOT ofthe Main System. The Distribution Unit not only provides forinterconnection of the Main System to a selected LCP but also regulatespriorities among LCP's for the access to Main Memory.

The invention herein particlarly claimed within the LCP-I/O Subsystem isa peripheral controller which is called the Line Control Processor whichcan process and execute data-transfer instructions in addition tostoring and buffering data thus to prevent access-errors.

Some of the major objectives of the Line Control Processor I/O Subsystemmay be summarized as follows:

To relieve the Central Processing unit from getting involved inmonitoring and controlling data transfers between the System's MainMemory and a large number of peripheral units.

To increase the rate of data transfer between a variety of differentperipheral units all connected to the Main System having a Main Memoryand Processor. This includes transfers from the Main Memory to anyindividual peripheral in this system and vice versa.

To provide an Intelligent I/O Interface control unit (Line ControlProcessor) which will relieve the Central Processor of many burdens andwhich will be responsive to the needs of various peripheral units foraccess to the Main Memory.

To provide an Intelligent Interface I/O control unit which can receivean I/O instruction from the Central Processing unit and thenindependently continue in regard to controlling, monitoring, andexecuting this instruction so as to accomplish data transfer betweenMain System Memory and any specifically desired peripheral unit. This isdone asynchronously as the needs and the requirements arise. Theinterface unit (LCP) also handles the error-checking of all word andmessage block transmissions in addition to keeping the Main Systeminformed of the status of any data-transfer cycle, as to itscompleteness, incompleteness, error-status. The Line Control Processoralso monitors requests from a peripheral unit for access to Main Memoryand informs the Main System of "busyness" of the peripheral unit or itsunavailabilty.

To permit easy modular system expansion the I/O Subsystem of the CentralProcessing unit servicing a plurality of terminal units is setup suchthat the interface units (Line Control Processor) are organized in BaseModules in groups of eight units. Each module has a Distribution CardUnit which interfaces the group of eight Line Control Processors to theMain System via the IOT of the Main System. The Distribution Unit canthus set priorities as between any one of the eight Line ControlProcessors in the Base Module. Further, when a plurality of Base Modulesoccur in the System then the Distribution Unit of each Base Module canbe given a priority ranking (designated global priority) as between thepriority rank granted to any given Base Module, within the full set ofBase Modules. Thus, another object of the I/O Subsystem involved is toprovide arrangements for setting up Global Priority (priority as betweenBase Modules in the System) and also Local Priority. (Priority as toprecedence status of each Line Control Processor in the group of eightLine Control Processors in the Base Module).

To eliminate "access errors" so that all the data required at any giventime for the Main System (that is, a message length block of data) isalways transmitted and error-checked in one complete cycle withoutinterruption (except under emergency conditions).

To permit the rapid completion of a data-transfer operation as betweenthe System's Main Memory and a given peripheral unit, withoutinterruption or incomplete data-transfer, once a communication channelis established (except for certain emergencies).

To provide the Main System with the current status of any Line ControlProcessor at all times and the results (complete, incomplete or inerror) of any given data-transfer cycle.

To provide modular building blocks for facilitating the expansion of theSystem by increasing the number of peripheral devices that can beincluded in the System in a simple economical fashion.

To provide an I/O Subsystem whereby the Central Processor is relieved ofexecuting I/O data-transfer cycles and this work load is distributedthroughout the system via I/O control units (Line Control Processors)grouped in modular block units (Base Modules).

BRIEF DESCRIPTION OF THE DRAWINGS

The I/O Subsystem described herein and the operative components involvedwill be better understood with reference to the following drawings ofwhich:

FIG. 1A is a schematic of a Central Data Processing System having twodifferent types of I/O Subsystems; the two I/O Subsystems are designatedas (a) the Central Control Subsystem (CC) with Input-Output Controllers(IOC) and (b) the Line Control Processor (LCP) Input-Output Sybsystem;

FIGS. 1B, 1C, 1D, and 1E, are schematics which indicate variouscomponents of the Central Control type of I/O Subsystem;

FIG. 2 is a schematic drawing of a modular unit of the LCP I/O Subsystemknown as the LCP Base Module showing its relationship to a variety ofperipheral devices;

FIG. 3 is a schematic drawing of the central processing unit of the MainSystem of the LCP Input/Output Subsystem;

FIG. 4A is a simplified schematic showing the basic connectiverelationships between the Main System, the Line Control Processor and aperipheral unit within the Line Control Processor I/O Subsystem;

FIG. 4B is a chart indicating various codes for the various instructionsexecutable by a Line Control Processor, LCP;

FIG. 4C is a chart showing how four informational digits (ABCD) areorganized such that a Line Control Processor can inform the Main Systemof operational results via a "Result Descriptor";

FIG. 5A is a chart of digital information (Descriptors) used by theInput-Output Translator (IOT) to generate Command Messages (C/M);

FIG. 5B is a schematic showing the data field boundaries of theDescriptors in FIG. 5A;

FIG. 5C is a block diagram of the Input-Output Translator (IOT) in itsrelationship to the Main System (Processor and Memory) and to the LineControl Processor (LCP);

FIG. 5C-1 is a block diagram showing the relationship of the 4 modulesof the Input-Output Translator to the Main System and to the Base Moduleunits holding the Line Control Processors; FIG. 5C-1a shows a moredetailed schematic;

FIG. 5C-2 shows the elements involved in the Input-Output Translatoraddressing scheme;

FIG. 5C-3 shows the buffers and elements involved in the InitiationModule for transferring the Descriptor Link;

FIG. 5C-4 shows the elements involved in the Descriptor Link Register;

FIG. 5C-5 shows the logic elements involved for receiving the DescriptorLink and placing it on the Descriptor Link bus;

FIG. 5C-6 shows the logical elements of the Connection Module for thedriver card enable;

FIG. 5C-7 is a diagram of the logic elements for the Connection Modulein regard to Bus selection;

FIG. 5C-8 shows the driver card enable logic of the Input-OutputTranslator;

FIG. 5C-9 shows the logic for the multiplexor inputs to provide SelectTerms;

FIG. 5C-10 is a logic drawing showing generation of the Transmit SelectLevels;

FIG. 5C-11 is a logic diagram showing the Output Buffer (OTB) data pathswitching;

FIG. 5C-12 is a logic diagram of the Data Transfer Module showing themodule select logic;

FIG. 5C-13 is a more detailed drawing of the logic in the Data TransferModule; FIG. 5C-13 is drawn on two sheets marked FIG. 5C-13A and FIG.5C-13B;

FIG. 5C-14 shows the logic elements involved in the Input-OutputTranslators base driver card and data paths;

FIG. 5C-15 is a flow chart showing the sequential operational steps ofthe Initiation Module of the Input-Output Translator; this flow chart ison two sheets marked FIG. 5C-15A and 5C-15B;

FIG. 5C-16 is a logic diagram showing the elements for loading the Bbuffer;

FIG. 5C-17 is a logic diagram showing the OP buffer shift control;

FIG. 5C-18 is a flow chart showing the sequential activity of theConnection Module of the Input-Outpt Translator;

FIG. 5C-19 is a logic diagram showing the initiate I/O signals and datalink bus generation;

FIG. 5C-20 is a "Poll Test" flow diagram showing the relationship of theInput-Output Translator to the other elements of the Subsystem;

FIG. 5C-20a is a logic diagram of the Base Module Distribution Cardshowing LCP address decoding;

FIG. 5C-20b shows logic for direction control;

FIG. 5C-21 is a flow chart showing the sequential steps of the DataTransfer Module of the Input-Output Translator; this flow chart is drawnon two sheets marked FIG. 5C-21A and 5C-21B;

FIG. 5C-21a is a detail logic flow of the Write Cycle while FIG. 5C-21bis a detail logic flow of the Read cycle;

FIG. 5C-22 is a diagrammatic sketch showing the Write cycle datatransfers between major registers;

FIG. 5C-23 shows the Read cycle data transfers from the Data TransferBus with the major registers;

FIG. 5C-24 is a flow chart showing how the Result Descriptor is handledand stored;

FIG. 5C-25 shows the "Poll Request" operation involving the relationshipof the Input-Output Translator to other sections in the Subsystem; FIG.5C-25a shows the priority encoding circuitry from the Line ControlProcessors; FIG. 5C-25a is drawn on two sheets marked FIG. 5C-25aA andFIG. 5C-25aB;

FIG. 5C-26 is a logic diagram showing the first stage of global priorityresolution in the Input-Output Translator;

FIG. 5C-27 shows the second stage of global priority resolution;

FIG. 5C-28 is a flow chart showing the sequential steps in the ReconnectModule of the Input-Output Translator;

FIG. 5C-29 shows the logic involved in the address selection by theReconnection Module of the Input-Output Translator;

FIG. 5D is a chart showing the information array in the IOT DescriptorRegister;

FIG. 5E shows the message level interface between the IOT and theDistribution Card Unit of the LCP Base Module;

FIG. 5F is a sketch of the IOT scratchpad memory;

FIG. 5G is a sketch illustrating the address memory scratchpad of theIOT (Input-Output Translator);

FIG. 6A is a logic flow diagram of the interface between the Main Systemand the Line Control Processor (LCP);

FIG. 6B is a generalized block diagram of a Line Control Processor;

FIG. 6C is another generalized block diagram of a Line Control Processorwith detail in regard to its data buffer memory;

FIG. 6D is a detailed functional block diagram of the Line ControlProcessor;

FIG. 6E is a diagram showing the intercooperating logic and controlsignals between the Input-Output Translator (IOT) of the Main System andthe Distribution Card unit for Line Control Processors within a BaseModule;

FIG. 6F is a chart showing the arrangement of a message block and thecomposition of a digital word;

FIG. 7A is a logic flow diagram of a Line Control Processor whichhandles a peripheral unit and shows the "status counts" for "Receipt ofInstructions";

FIG. 7B is a flow diagram showing how the Line Control Processor handlesa "Write" operation;

FIG. 7C is a flow diagram showing how a Line Control Processor handlesthe "Read" operation;

FIG. 7D is a flow diagram showing how the Line Control Processorlogically handles the Result Descriptor;

FIGS. 7E-1 and 7E-2 together form a logic diagram showing the overalllogic flow of the Line Control Processor.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The digital system described herein consists of a Processor, a Memory, aseries of Input-Output Controllers (IOC's) forming a first I/O Subsystemand a system of Line Control Processors (LCP's) that make up a secondI/O Subsystem. The Line Control Processors basically handle input-outputoperations for specific peripherals with minimal interfernce to mainprocessor operations. Further, no peripheral device is "hung up" waitingfor memory access, since the LCP for that peripheral is always readilyavailable to service its peripheral.

A substantial number of prior data processing systems utilize ahierarchical system of Main Memory in which a large capacity, slow bulkmemory must transfer information to a small high-speed processor memorybefore that information can be used. The presently described systemallows the Processor and the I/O Subsystem to directly access any areaof memory, and since the memory size may go up to one-million bytes, farmore information is available to the Processor without the imposition ofadditional I/O activity. This system may be provided with high-speed(250-nanosecond cycle time) bipolar memory together with an errorcorrection system. Bipolar memory is not only fast, but is inherentlymore immune to the type of errors that cause program failures. If anerror is detected, the error correction occurs during the normal memorycycle and there is no additional time required for a correction cycle.Various operating relationships between the processors main memory andother units of the present system may be found in a BurroughsCorporation publication entitled "Burroughs B 2800/B 3800/B 4800 series,MS-2 Reference Manual, Catalog 1090560, Copyright 1976".

Normally, I/O memory cycles account only for a small fraction of thetotal number of memory cycles available. However, during periods of highI/O activity, the probability of any two devices requesting the samememory cycle increases. When, due to simultaneous requests, a devicefails to get access to memory within a system-allotted time period, thenvaluable time is lost while the operation is retried. Furthermore,during periods of low I/O activity, many memory cycles are unused.

The I/O activity problems are solved in the present system bydistributing the I/O processing among a group of LCP's or Line ControlProcessors organized into Base Modules of eight LCP's each. In so doing,the Central Processor is only required to initiate the I/O activity andit takes no further role in the Input-Output (I/O) operation. TheCentral Processor initiates the I/O activity through a device called theInput-Output Translator (IOT).

The LCP, once initiated, can buffer large amounts of data and, in mostcases, an entire message block. At some point in the operation, the LCPrequests an access to memory and when the access is granted, LCPtransfers the information from its "word buffer" to the Memory at themaximum rate of memory operation. Now, if the requested access to memoryis not granted, the LCP continues to fill its word data buffer whilewaiting for an opportunity to access Memory. Thus, the peripheral deviceis now protected against no-activity since its data will be transferredto the buffer of the LCP, which then transfers it to the Main Memorywithout missing a memory access period.

The result of this method and system is that the peak loads imposed uponthe Memory by the demands of I/O activity are eliminated; instead, theI/O Subsystem utilizes those memory cycles that would otherwise bemissed. Since this method of I/O processing is more efficient, thesystem is more capable of a higher input-output (I/O) data transfer rateand can also support more I/O devices.

In the instant computer system wherein there are two categories ofInput-Output Subsystems, that is, the first Subsystem of I/O controlsand the second Subsystem of an Input-Output Translator working with agroup of Line Control Processors, the control of the system isfacilitated by the use of "descriptor" information which is passed amongthe various units.

A "Result Descriptor" is a report to the Main operating system thatdescribes the manner in which an operation was completed or the reasonwhy the operation could not be completed. The Result Descriptors for theProcessor and for the I/O control systems are 16 bits (one word) long.The LCP Result Descriptors may be longer than one word, however, andeach bit in the Result Descriptor represents the status of somecondition that is to be reported to the main operating system.

The LCP's (Line Control Processors) and the I/OC's (I/O Controllers)always write Result Descriptors upon completion of an operation; theProcessor writes a Result Descriptor only if an error condition wasencountered. Result Descriptors are written into predetermined locationsin Memory; for the Processor, the location is address 80, for example.The use of "Result Descriptors" is described in U.S. Pat. No. 3,512,133.

The Result Descriptors for the LCP's and the I/OC's are written intolocations beginning at the address specified by the equation (CH×20)plus 200, where CH is the channel number of the initiated device. TheIOT Result Descriptor is written into address 260. After the ResultDescriptor has been written, an interrupt is generated.

LCP Result Descriptors, R/D: Upon the completion of its assignedoperation, the LCP stores a Result Descriptor, which describes to theProcessor the manner in which the operation was completed. An LCP ResultDescriptor may consist of one, two, or three 16-bit words. The firstResult Descriptor, R/D, is stored in Memory at the location specified bythe equation (CH×20) plus 108, where CH is the channel number of an LCP.If more than one word of Result Descriptor information is to be written(extended Result Descriptor), the additional words are stored in theaddress memory of the IOT. As shown in the table I below, the first LCPResult Descriptor word is preceded by a 1-word link and the channel(IOT) Result Descriptor. Typically, the link is used by the operatingSystem as an address to the next Result Descriptor to be examined. TableII shows the basic word format for a "data" word having 4 digits, A, B,C, D, where each digit has 4 bits and each character has 8 bits. Symbolsare used to designate parts of each digit, as A8, A4, A2, A1, etc.

                                      TABLE I                                     __________________________________________________________________________    Result Descriptor                                                              ##STR1##                                                                     Channel/LCP Result Descriptor Location in Memory                              __________________________________________________________________________

                  TABLE II                                                        ______________________________________                                        Data Word                                                                      ##STR2##                                                                 

The table III below indicates the format for the I/O descriptor which isnormally stored in Main Memory and then accessed in order to regulate aparticular type of Input/Output operation. As will be ssen there arefour syllables, wherein each syllable is composed of 6 digits. Thesedigits are numbered D1-D6, D7-D12, D13-D18, D19-D24, to indicate therelative positions of each digit. In syllable 1, the digits D1 and D2always specify the type of input/output operation to be performed andare generally called the "OP-code". Digits D3-D6 are referred to as"variant digits" in that they specify the various options that aspecific input-output operation can incorporate.

Syllable 2 contains the address of the most significant digit (MSD) ofthe Main Memory section which is used in this particular input/outputoperation as a memory buffer area. This buffer area is referred to asthe beginning address. Syllable 3 contains the address of the leastsignificant digit plus 1 (LSD+1) of the input/output core memory bufferarea which is referred to as the "ending address". The most significantaddress and the least significant address plus 1 represent the maximummemory boundary limits of a record being transmitted. The length of therecord may or may not utilize the entire area within this limit. But anattempt to exceed this limit causes termination of data transmission tothat area.

Syllable 4 is used only for disk file descriptors and contains the diskaddress.

The length of the record may or may not utilize the entire area withinthe beginning address and ending address limits. As stated, an attemptto exceed this limit causes termination of data transmission to thatarea. For example, punch cards may be read into an area greater than 80characters, that is, with a MSD and an LSD+1 at 80 characters apart, orthey may be read into an area less than 80 characters; for example, therecord area defined in a particular object program reflects 40characters in a card reader record. Data within columns 1 through 40 ofthe punch card are stored in the record area of core memory allocated byMSD and LSD+1.

                                      TABLE III                                   __________________________________________________________________________    I/O Descriptor Format                                                          ##STR3##                                                                      ##STR4##                                                                     __________________________________________________________________________

System Description: (General):

An I/O Subsystem is provided as part of a digital system environment tosupply means of communication between a central data processing systemand a variety of peripheral devices which are attached to and workwithin the system. The peripheral devices which work with the overalldigital system herein vary from mass storage devices, such as disks ordisk packs, to system control devices such as the operator's supervisoryterminal, or to a variety of other peripheral devices such as printers,card readers, card punches, magnetic tape storage devices, and so on.

The I/O Subsystem described herein can be divided into two majorsubsystem categories, based on the method by which the variousperipheral devices are controlled. The first category uses a methodwhich employs I/O Controllers (IOCs) working in conjunction with theProcessor and a Central Control to handle I/O activity. The secondcategory uses an Input-Output Translator (IOT) in the central processingunit which works with individual units called Line Control Processors(LCP's). The units known as Line Control Processors are the deviceswhich establish a communication path from the System (Main Memory andProcessor) to a specific peripheral device. Once the communication pathis established, the LCP can accept data from, or pass data to, thespecific peripheral device, for later transmission to the Main System.Since each LCP has a built-in data buffer, then data can be transferredto and from the given peripheral device at the comparatively low speedrate of the device; however, when the data buffer of the LCP isconnected to transmit to the Main System Memory and Processor, the datacan be transferred to the Main System at the highest rate allowed by theMemory of the Central System.

The first category of I/O Subsystems which use IOC's as an interfacefrom a peripheral to the Main Memory and Processor has a Central Control(CC) unit which links the I/O channel and IOC with the Central Processorand Memory. These Input-Output Controllers accept instructions from theProcessor and they return data information involving the result of whathappened regarding that particular instruction. This result informationis placed in a specified location in the Main Memory.

The use of a Central Control unit such as element 12 of FIG. 1A and thecooperative I/O control units 13_(a), 13_(b), is described in technicalmanuals published by the Burroughs Corporation entitled "B 3500,Processor, Memory, Central Control" Technical Manuals Nos. 1028958,1028982, 1028974, 1038650. The use of these elements is furtherillustrated in U.S. Pat. No. 3,688,273. The use of the priority controllogic feature 10_(pc) of FIG. 1C and FIG. 1D is illustrated in U.S. Pat.No. 3,633,163.

In the second category of I/O Subsystem is the system wherein theProcessor and Main Memory communicate, via an Input-Output Translator(IOT), to a group of LCP Base Modules, each Module of which constitutesa unit supporting a group of 8 Line Control Processors (LCP's). Thus, aninstruction from the Processor is translated by the IOT into aspecialized set of commands which is acceptable to individual LCP's.After an LCP accepts instructions from the IOT, it will then report backcertain "result information" which is stored in a specified location inthe Main Memory.

Thus, in this second I/O Subsystem, all communications between the mainsystem Processor and Memory over to a specified peripheral device arecontrolled by an LCP which is uniquely suited to that particularperipheral device.

When a Line Control Processor, LCP (or an Input-Output Control meanshaving a Central Control) is installed, it is assigned a unique numbercalled its "channel number". For I/O Controls this number corresponds toa word of scratchpad memory located in the Processor. For Line ControlProcessors (LCP's) this "channel number" corresponds to a word ofscratchpad memory in the Input-Output Translator (IOT).

To accomplish an input-output operation in the system, an I/O request isinitiated by an Initiate I/O Instruction which tells the Processor whereto find the appropriate I/O Descriptor in the Main Memory and also whichchannel number it is intended for. The I/O Descriptor contains the OPcode and also the variants for the kind of I/O operation selected, andthe beginning (A) and ending (B) Main Memory address of the memory areainvolved.

The Processor accesses this I/O Descriptor and then sends the OP codeand its variants to the selected IOC (first Subsystem) or to the IOT(second Subsystem). The IOC or the IOT verifies the OP code andsignifies acceptance or rejection of the request.

In the first Subsystem the Processor then loads the beginning (A) andthe ending (B) addresses into a local register and informs the IOC thatthe addresses are available. These particular addresses are transferredby the IOC into the scratchpad memory location for that designated I/Ochannel.

In the second Subsystem the IOT accesses the A and the B addressesdirectly from the memory address lines leading to the Processor's "localregister" (10_(pr), FIG. 3) at the time of transfer from Main Memory andthus the IOT loads its own local scratchpad memory 10_(ps).

The access to Main Memory is shared by the IOT, the Central Control andthe Processor. The highest priority is shared by the IOT and the CentralControl. The timing may be so arranged that each Central Control isguaranteed and limited to every fourth memory cycle (at, for example, 8MHz.). The IOT is guaranteed the remaining cycles. When The CentralControl is not requesting memory, then the IOT can take all the memorycycles. The Processor takes all memory cycles available on a lowestpriority basis.

Thus, I/O communications in the system require that the Processorexecute an Initiate I/O Instruction (which may be designated, forexample, as OP=94). This Initiate Instruction specifies the channelnumber of the requested device and also the location of the I/ODescriptor in Main Memory. The I/O Descriptor specifies the action to betaken by the peripheral device and specifies the boundaries in Memory ofthe data field. The Descriptors, and the manner in which they areexecuted, vary, depending on the method by which the peripheral deviceis controlled.

If an Initiate I/O Instruction is executed for a channel containing anI/O Control (first I/O Subsystem), then the Processor sends theDescriptor OP code, variants and a C address (if used) to the I/OControl. The A (beginning) and B (ending) addresses of the Descriptorare stored in the Processor's I/O channel address memory 10_(pam). TheI/O Control verifies that the OP code is valid, then signals theperipheral device that a data transfer is to begin.

As was previously discussed, the embodiment of the present digitalsystem involves a duality of Input/Output Subsystems. The second ofthese involve a Central System with Input-Output Translator (IOT), aBase Module having a plurality of Line Control Processors (LCP) and aplurality of peripheral units; the first I/O Subsystem involves, as seenin FIG. 1A, a Central Control unit 12 which interfaces with a pluralityof I/O controls 13_(a) and 13_(b) which interface with a plurality ofperipheral devices 14_(a) and 14_(b), etc.

The following discussion will involve the first I/O Subsystem involvingIOC's with Central Controllers, CC. The FIG. 1B shows the system ofconnecting the I/O channels with the Processor, 10_(p), and the MainMemory 10_(m) through the Central Control 12. Logic levels are generatedin each I/O channel 100, 101 (FIG. 1C) and combined by Central Control12 before being sent to the Processor 10_(p) and the Main Memory 10_(m).Other logic levels are generated by the Processor, and within theMemory, and distributed by Central Control 12 to each I/O control suchas 13_(a), FIGS. 1A and 1B. There are also logic levels which passthrough the Central Control 12 with the Central Control performing asthe connecting block between the Processor 10_(p) and I/O channels.Priority logic, 10_(pc) of FIG. 1C, determines which of the I/O channelswill be allowed access to the Main Memory 10_(m), should more than onechannel need access at the same time.

As seen in FIG. 1C, there is included, as part of Central Control 12, aplug in translator which is capable of translating BCL (Burroughs CommonLanguage) data to or from EBCDIC (Extended Binary Coded DecimalInterchange Code) as it goes to or comes from the Core Memory 10_(m).The I/O Control units, 13_(a), 13_(b), FIG. 1A, request Central Control12 to use the translator, 12_(t), FIG. 1C, or to bypass it. Thetranslation takes place as data is transferred between the I/O Controlunit, such as 13_(a), and the Main Memory 10_(m). Additional time is notrequired for I/O operation even though translation is necessary. Thetranslator logic translates incoming Burroughs Common Language (BCL)data into EBCDIC (Extended Binary Code Decimal Interchange Code) data orthe outgoing EBCDIC data into Burroughs Common Language (BCL). ThoseEBCDIC codes which are not assigned a BCL code, will cause to begenerated a code for a BCL symbol "?".

The Central Control 12 functions as an interface between an I/O channeland the Main Memory 10_(m) during system operation, as seen in FIGS. 1Band 1C. It determines the priority of memory accesses, should more thanone channel need access, and it translates data coming to the I/Ochannel, as 100, from Memory 10_(m) or from the I/O channel to Memory.The Central Control correlates various functions of the channels. Thesequence of events is initiated by the Processor 10_(p) when an I/Ochannel is needed.

When the program being performed has need of a peripheral unit such as14_(a) or 14_(b) of FIG. 1A, the Processor 10_(p) executes the "InitiateI/O Instruction". This instruction reads an I/O Descriptor from Memory10_(m) and then sends the necessary information to the I/O channel, 100,through Central Control 12. This information contains the type ofoperation (OP code) and the variant information. The remaining portionof the I/O Descriptor including the beginning (A) and ending (B)addresses, is stored in Address Memory, 10_(pam), FIG. 1C, of theProcessor 10_(p). The channel is selected by the channel designate level(CDL) as seen in FIG. 1B, which line comes from the Processor 10_(p).

Once all the information is available, the I/O channel, 100, is releasedby the start channel bus (STCB), FIG. 1B, to operate independently. Whenthe I/O channel has been released, it operates as another processor andshares the Main Memory 10_(m) with the main Processor 10_(p) or otherchannels (FIG. 1C).

If the operation being performed involves an "input type" peripheralunit 14_(i) such as a card reader, the data is received by the I/Ochannel 100 seen in FIG. 1C, and the data is stored in a buffer C_(o)within the I/O channel 100. The I/O channel then requests access to MainMemory 10_(m) via Central Control 12. This request is processed by thepriority logic 10_(pc) (one type of which is illustrated in U.S. Pat.No. 3,633,163) which controls other requests at the same time. Onceaccess to Memory has been granted to the channel, the information istransferred to Memory 10_(m). The information may or may not betranslated depending upon the I/O Descriptor. The information is thenwritten into the Main Memory 10_(m) at the location specified by thebeginning (A) and ending (B) addresses in the Address Memory, 10_(pam).

If it is desired, at some point, for data or information to betransferred out to a peripheral terminal unit, this is called an"output" operation, FIG. 1D. If an "output" operation is beingperformed, a similar sequence of events occurs as before, except thatdata goes from the Main Memory 10_(m) to an I/O channel such as 102 ofFIG. 1D. Then when a peripheral unit as, for example, a printer 14_(p)needs data, the memory access request is made to the Central Control 12via the I/O channel, 102. When priority is granted to the channel, thedata is read from Main Memory 10_(m) from the address specified by thebeginning and ending addresses located in the Address Memory 10_(pam) ;this data is then transferred to the I/O channel buffer C₂ through thetranslator 12_(t) (or bypassed around the translator depending upon theI/O Descriptor). As seen in FIG. 1D, the data is then transferred to theperipheral unit, such as 14_(p).

As seen in FIG. 1E the Central Control 12 provides an interface to/fromthe I/O channels, the Processor 10_(p), and the Core Memory 10_(m).Control information from the Processor 10_(p) is sent to the CentralControl 12, where it is distributed to each I/O channel as 100, 101,etc. The Central Control 12 handles all of the Core Memory requests madeby the I/O Control units in this first I/O Subsystem. Data from each I/Ochannel, which is to be written into Core Memory 10_(m) is placed on theMemory Write Bus by the Central Control 12, and data which is to be readfrom the Core Memory 10_(m) is placed on the Core Memory Read Bus anddistributed to each I/O channel.

When a request is made by an I/O channel unit, the Central Control 12will obtain the Core Memory address from the Address Memory locationreserved for that specific I/O channel. This address is used to accessMain Memory 10_(m) and the memory cycle is then initiated. The memorycycle could be either a "Read" or "Write" depending on the specific I/Ooperation.

When the Processor 10_(p) requests a memory access, the memory addressinvolved is obtained from the Address Memory 10_(pam) located in theProcessor 10_(p). This address is used to access Main Memory 10_(m), andthe memory cycle (either a read or a write) is initiated.

Since only a single memory access can be made at a given moment,multiple memory requests must be handled individually, and this handlingis accomplished automatically via Priority Control 10_(pc) (FIG. 1C, 1D)by Central Control 12, as previously discussed. Each Central Control 12contains "priority logic" 10_(pc) which is established or changed by afield engineering adjustment. As I/O channels are added to the CentralControl 12, they are also added to the priority network. The Processor10_(p), in this case, has a lower priority than a Central Control 12.The highest priority request is granted first, and as soon as it iscompleted, the next highest request is automatically granted. Thisprocess is repeated until all of the multiple requests are handled. Therequests are alternately granted to each Central Control unit (whenmultiple Central Controls are used) depending on which control wasgranted the last request. If a Central Control does not want the access,then it is granted to the Processor 10_(p).

During the course of a data transfer operation within the first categorySubsystem, the I/OC (Input/Output Controller) may perform severalfunctions depending on the OP code, the variants, and the type ofperipheral device. Typically, the I/O Controls have the ability tobuffer only one byte or at most one word. Thus, when the data buffer ofa control is loaded, the I/O Controller or I/O Channel Unit 100, 101,102, must request a memory access; therefore, the rate at which data istransferred to or transferred from the System is controlled primarily bythe speed rate at which the peripheral device can read or write. Thesecond I/O Subsystem using Base Modules with Line Control Processorsdoes not have this speed limitation.

When the I/O Controller requests a memory access, it is, in effect,asking the Processor to perform a series of operations; these operationsinclude: (a) the transfer of the data field address from the processor'sI/O channel address memory to the local address register; (b) theinitiation of a memory cycle; (c) and the restoration of the data fieldaddress to the address memory of the channel. The I/O Controller alsoindicates to the Processor the amount by which the address must beincremented so as to point at the next field location. Upon completionof the operation, the I/O Controller builds a Result Descriptor (R/D)indicative of how the operation was effectuated, then the I/OC storesthe Result Descriptor in a reserved memory location, after which it setsthe Processor Interrupt flip-flop.

In the second category of controlling I/O activity, use is made of anInput/Output Translator (IOT) interface unit which is located in thecentral processor unit 10. The IOT interfaces with a group of LineControl Procesors (LCP) which are installed in LCP Base Modules. Up toeight LCP's may be housed in an LCP Base Module. The Base Module for theLCP's holds up to as much as eight LCP's. The LCP is an intelligentinterface unit which establishes a buffered data-transfer path betweenthe peripheral device involved and the main system of Processor andMemory. This communication path is established by the LCP upon receiptof a Command Descriptor (C/D) from the IOT which has translated anoriginal I/O Descriptor into a specialized Command Descriptor for theLCP.

Since each LCP has a large "data buffer" of, typically, 256 words, thendata can be transferred to and from a specific peripheral device at thecomparatively low rate of the device; however, when the data buffer isfull, data can be transferred to the Main System at the highest rateallowed by the memory speed of the Main Memory, which is at a fast rate.

The LCP Base Module, which houses up to eight LCP's, operates inconjunction with the IOT to establish connection to and to initiateoperation of a particular LCP. The LCP Base Module also supplies thetiming signals, the maintenance logic, the power supply and coolingwhich is supportive of each group of individual LCP's.

The IOT is that portion of the central processing unit which, uponreceipt of an I/O Descriptor, works in conjunction with the LCP BaseModule to establish connection to a particular LCP in the channelspecified by the Initiate I/O Instruction. The IOT translates the I/ODescriptor to a form (Command/Descriptor) recognizable to the LCP, and,when connection is established, passes the translated descriptor to theLCP, after which data transmission may begin. During the time that thedata is being transferred between the LCP and the Main System, then theIOT, upon demand from the LCP, requests memory accesses, addressesmemory, then modifies and compares the data addresses. Further, the IOTcontrols the routing of data between the selected LCP and the MainSystem, and it performs translations (ASCII/EBCDIC) of the data if sorequired. Upon completion of an operation, the IOT accepts R/D (ResultDescriptor) information from the LCP, and then stores the ResultDescriptor in a predetermined location.

The LCP system configuration allows up to 68 I/O channels. In the I/OControl Subsystem there may be two CC's (Central Controls) with eightI/O Controllers each for a total of only 16 channels.

In the LCP subsystem, however, there may exist up to eight LCP BaseModules per single IOT. Each Base Module may service and carry up toeight LCP's. Thus, one IOT may serve as many as 64 LCP's. A MultiplexAdapter may be used to provide the effect of "two" IOTs connected tocommon LCP Base Modules. This configuration may be used to improve I/Oband pass to the Main Memory.

The entire I/O System has channel addresses which must be unique inthemselves. Access to Main Memory is shared by the IOT, the CentralControl and also the Processor.

In FIG. 1A there is seen an overall system diagram showing the dualcategories of I/O Subsystems. The first I/O Subsystem is made of CentralControl 12 which supports I/O Controls 13_(a) and 13_(b) which connectrespectively to peripheral devices 14_(a) and 14_(b). This first I/OSubsystem (using Central Control) is connected to the Main System 10 bymeans of interconnecting bus 11.

The Main System 10 is shown comprising a Main Memory 10_(m), the CentralProcessor 10_(p), the Memory Control 10_(c), and the Input-OutputTranslator 10_(t). A PCC (Peripheral Control Cabinet) interface 10_(i)connects via bus 5 to a Peripheral Control Cabinet 6 which houses theCentral Control and the I/O Control units of the first I/O Subsystem.

The Input-Output Translator 10_(t) of the Main System, FIG. 1A, forms asecond I/O Subsystem through the use of cabinets shown as LCP cabinetnumbers 0, 1, 2, designated as 16₀, 16₁, 16₂. Each of the LCP cabinetssupports three LCP Base Modules, for example, base cabinet 16₀ carriesBase Modules 20₀, 20₁, 20₂ ; while LCP cabinet 16₁ supports LCP BaseModules 20₃, 20₄, and 20₅ ; likewise, LCP cabinet 16₂ supports LCP BaseModule 20₆, and 20₇. Each of the individual LCP Base Modules isconnected to the IOT 10_(t) by means of message level interface cables(MLI) 15, each of which is made up of 25 lines.

Referring to FIG. 2, a typical LCP Base Module 20₀ is shown in greaterdetail. The Base Module 20₀ is composed of eight Line Control Processors(LCP's) 20₀₀ through 20₀₇, in addition to a common Distribution Card20_(0d), a common Maintenance Card 20_(0m) and a common Termination Card20_(0t). The Distribution Card 20_(0d) connects to one set of themessage level interface cables 15 which connect to the IOT 10_(t) (alsosee FIG. 5E).

Each individual Line Control Processor is seen connected by output linesto a particular peripheral device, wherein, as seen in FIG. 2 the LCP's20₀₀ through 20₀₇ respectively connect to peripheral devices 50, 51, 52,53, 54, 55, 56, 57.

While each LCP of the Base Module may be slightly different in certainaspects in order to accommodate the idiosyncrasies of each particularperipheral device which the LCP handles, each LCP is of basically thesame design and functional capability. With reference to FIG. 2, atypical example of each LCP is seen in the LCP 20₀₆ which is seen havinga System Interface 21_(si), a Device Interface 22_(di) and having a WordBuffer 25₀₆ which is typically capable of holding 256 words.

Referring to FIG. 3 there is seen a more detailed block diagram of theMain System as it relates to the I/O LCP Subsystems. The Main System 10has a Main Memory 10_(m) in which there is a reserve portion 10_(mi) forI/O Descriptors and another reserve section 10_(mr) for ResultDescriptors. In addition the Main Memory 10_(m) has another reserveportion 10_(mc) for storage of channel numbers. The I/O Descriptors,Result Descriptors, and Channel Numbers are information used by theSystem for control and for recognition of the status of operations.These will be described in detail hereinafter.

The Processor 10_(p) has a local register 10_(pr) which is useful forstoring information for the IOT. The Input-Output Translator 10_(t)holds a channel scratchpad memory 10_(ps).

The local register 10_(pr) of the Processor 10_(p) is used for storingthe beginning (A) and the ending (B) addresses of the appropriate I/ODescriptor. (In the case of the first I/O Subsystem using a CentralControl, FIG. 1A, the I/O C causes these addresses to be transferredinto a temporary storage location called channel scratchpad memory orchannel address memory). In the case of the second Subsystem using theIOT, the IOT accesses the A and B addresses directly from the memoryaddress lines leading to the local register 10_(pr) of the Processor.The channel scratchpad memory 10_(ps) for all 64 LCP's is contained inthe IOT. The channel scratchpad memories will also contain the requiredchannel numbers.

With reference to FIG. 4A and the transfer of information as between themain system 10 and a typical LCP 20₀₀, a brief look at these informationwords and their functions will indicate the nature of the operatingrelationship.

Command Descriptor (FIG. 4A)

The Command Descriptor (C/D) is a modified form of the I/O Descriptor.The I/O Descriptor is the information residing in Main Memory 10_(m),FIG. 1 (and specifically in 10_(mi) of FIG. 3), which provides data andinformation as to the type of Input-Output operation to be accomplished.The modification of the I/O Descriptor is accomplished by the IOT,10_(t) (Input-Output Translator, FIG. 1) which receives the I/ODescriptor from the System Memory 10_(m), retains a portion of theinstruction, and then transmits the applicable portion to the LCP 20₀₀as a Command Descriptor.

The Command Descriptor is a 17-bit word, A, B, C, D, (FIG. 4B)consisting of an OP code digit (A), variant digits 1 (B), 2 (C), and 3(D), and a parity bit. However, the LCP 20₀₀ makes use of only the OPcode digit and variant digit 1 for instructional purposes. Variantdigits 2 and 3 are always equal to 0. The OP code digit (A) defines thebasic operation to be performed by the LCP 20₀₀, and the variant digit 1(B) specifies modifications of the basic operation. No memory addressinformation is sent to the LCP; the System Memory address functions areaccomplished by the IOT 10_(t). FIG. 4B contains the Command Descriptorcodes for all operations that can be performed by the LCP. Theseoperations include: Write, Read, Write Flip Read, Test, Test Enable,Conditional Cancel, and Echo. These operations will be later describedhereinafter.

Descriptor Link (FIG. 4A):

The Descriptor Link (D/L) consists of two 16-bit information wordsaccompanied by a longitudinal parity word (LPW). The Descriptor Link isexchanged between the IOT 10_(t), (FIG. 1) and a LCP, as LCP 20₀₀, atspecific times during communication between the two units. The contentof the Descriptor Link is shown in the following table. The data bitswhich are not listed are reserved for future use.

                  TABLE IV:                                                       ______________________________________                                        Descriptor Link (also see FIG. 5D)                                            Data Bit               Designation                                            ______________________________________                                        A8            Inhibit Acess to system memory.                                 A2            ASCII Translation Required                                      C2            Base Module Address: 4 bit.                                     C1            Base Module Address: 2 bit.                                     D8            Base Module Address: 1 bit.                                     D4            LCP address: 4 bit.                                             D2            LCP address: 2 bit.                                             D1            LCP address: 1 bit.                                             ______________________________________                                    

Data (Intelligence) (FIG. 4A)

These are the bidirectional communication lines for transfer of datafrom the System 10 over to the LCP such as 20₀₀ for eventual transfer toa peripheral unit such as 50; or otherwise for transfer of data from theperipheral unit 50 over to the LCP 20₀₀ and thence to the System 10 forstorage in Memory 10_(m). In FIGS. 1 and 3, these channels would be themessage level interface (MLI) 15. Data transmission between the System10 and the LCP 20₀₀ is in the form of words (Table II) except forcertain transmissions which arelimited to a single character or fortransmissions ending in an odd number of characters. Each "data word" iscomposed of two 7-bit ASCII characters and a single parity bit. Databits A8 and C8 are not used, (Table II).

It should be noted in regard to the Commnd Descriptor, that afterreceipt of a Command Descriptor, but prior to execution of an operation,the LCP 20₀₀ receives the Descriptor Link from the IOT 10_(t) and storesit in the LCP buffer 25₀₀ (FIG. 2). When the LCP 20₀₀ disconnects fromthe System 10, then reconnects for further communication, the DescriptorLink is returned to the IOT 10_(t) to identify the LCP and the operationin progress.

Result Descriptor (FIG. 4A)

A Result Descriptor is generated by the LCP 20₀₀ and forwarded to theSystem 10, after the instruction contained in a Command Descriptor (C/D)is executed, or when an error occurs during receipt of a CommandDescriptor or a Descriptor Link. The Result Descriptor is sent to theSystem 10 by the LCP, in a 16-bit word format, with a parity bit. FIG.4C shows the 16-bit format for a Result Descriptor, wherein digits A, B,C, D will each have 4-bits.

Longitudinal Parity Word (FIG. 4A)

The Longitudinal Parity Word (LPW) is a 16-bit word representing thelongitudinal parity of each transmission between the System 10 and theLCP 20₀₀. An LPW is accumulated in both the IOT 10_(t) and the LCP 20₀₀during a transfer of information between the two units. An LPW registeris provided in the LCP 20₀₀ wherein accumulation of the LPW by the LCP20_(oo) consists of applying each word being transferred to the input ofthe LPW register and performing a binary add operation without carry(exclusive OR function). Then at the end of a data transfer, theexclusive OR function is again performed between LPW's of the sendingand the receiving unit. If no errors have occurred, both LPW's will beidentical, and the resultant value in the LPW register will be "all0's".

Input-Output Translator (IOT) (FIG. 5C)

The IOT 10_(t) translates the system I/O Descriptors into theappropriate operational messages relevant to each LCP. In return theresult messages from the LCP in the form of Result Descriptors are nottranslated by the IOT, but are stored directly into Memory 10_(m) at10_(mr) as transmitted by the LCP's. The IOT performs all theinformation transfers between the LCP's and the Main Memory 10_(m)necessary to support the input-output capability of the second I/O LCPSubsystem.

The I/O Descriptors, which are sent to the IOT from Memory 10_(m), areshown in FIG. 5A. Section 1A of this figure shows the descriptors usedby the IOT to generate command messages C/M for the LCP. These can alsobe referred to as Command Descriptors C/D. Section 1B indicatesdescriptors used by the IOT. Operations 40 through 58 are translatedinto LCP OP codes and sent to the LCP's in "message" format. The "L"digits in the variant field carry information used in the variant digits(B, C, and D) of the descriptor information sent to the LCP's. TheS-digit is used by the IOT as shown by the note of section 1A of FIG.5A.

Each operation shown in FIG. 5A has two OP codes; the difference is inthe number of addresses used by the LCP. The first digit of the OP codedesignates the number of addresses required. For example, a value of 4designates two-address operation (except "test" which has none); a valueof 5 for the first digit of the OP code designates three addressoperation. The second digit of the OP code is mapped into the actual OPcodes sent to the LCP's as the "A" digit.

FIG. 5B shows the data field boundaries of operations going in theforward direction and in the backward direction. (Forward=System toLCP).

FIG. 5A also shows the four types of standard operational messages usedfor controlling the LCP's: these are

1. Read

2. Write

3. Test

4. Echo

The specific descriptor information is obtained in the form of variantswhich accompany these OP codes. "Read" and "Write" require system memoryaccess. All operations which do not transfer data are considered "Test".Thus, a "Test" is defined as an operation which results in the IOTreceiving result information only. "Echo" is a confidence test operationwhich causes the LCP to accept a buffer load of information from theSystem 10 and then return it to the System 10 for check-out.

All communications between the Main System 10 and the LCP is over astandard message level interface 15 (MLI). This communication betweenthe IOT and the various LCP's is accomplished by a standard flowdiscipline which is common to all LCP's.

In FIG. 5C the IOT 10_(t) receives I/O Descriptors from the Processor10_(p). The IOT then connects via Distribution Unit 20_(od) to therequested LCP channel and sends the translated descriptor information(Command Descriptor C/D) in a message format which indicates the LCP'stask. The IOT then becomes LCP "status driven". This means that the IOTresponds to the various LCP states (including memory requirements) asindicated via the control lines between the LCP and the IOT FIG. 4A. TheIOT manages the transfer of information between Main Memory and theLCP's. The LCP's memory requirements drive the IOT for all datatransfers except that of initiation.

Either the IOT or the LCP can initiate a connection to Main Memory10_(m). The IOT initiates a Main Memory connection to an LCP (and itsassociated peripheral) by performing an algorithm which is called a"Poll Test". On the other hand, the LCP initiates a connection to IOTand Main Memory by an algorithm called a "Poll Request". Once the LCP isconnected, it indicates its status via the control lines of FIG. 4A. AnLCP which is initiating a "Poll Request" must compete with the otherLCP's in the system; a connection to Main Memory 10_(m) is granted on apriority basis which will be described hereinafter. During an operation,the IOT 10_(t) may disconnect from one LCP in order to service anotherLCP.

The message transmissions between the IOT and the LCP involve data andcontrol messages which are transmitted 16 bits at a time along with avertical odd parity bit. Following the last message, a 16-bitlongitudinal odd parity word (LPW) is transmitted accompanied by avertical odd parity bit. Parity is checked by both the IOT and the LCP.If a parity error is detected by the LCP, then the LCP reports this inits result information transmission (Result Descriptor) and halts theoperation. If the IOT detects a parity error, it is inserted in the LCPResult Descriptor.

The Input-Output Translator 10_(t) (IOT) consists of four majorfunctional sections, each concerned with one particular aspect ofinput-output operation. These functional sections are shown in FIG. 5C.Further, the operating relationships between the IOT and the Main System(Processor and Main Memory) and also the LCP and the peripheral device,are also shown.

Referring to FIG. 5C, the Input-Output Translator 10_(t) communicateswith the Processor 10 and the Main Memory 10_(m). The IOT 10_(t) alsocommunicates with a selected LCP as Line Control Processor 20₀₀ and theperipheral device 50. A series of control lines in FIG. 5C are shownfrom the Processor 10 to the Initiation Module 10_(ta), the ConnectionModule 10_(tb), the Data Transfer Module 10_(tc) and the ReconnectionModule 10_(td).

Initiation Module

The Initiation Module 10_(ta) accepts the descriptor information,including the addresses, from the Processor 10, and then translates thedescriptor OP code and assembles the information into a form usable bythe LCP 20₀₀. The A and the B addresses of the descriptor are stored inthe IOT scratchpad memory 10_(ps), FIG. 3, which has locations reservedfor each designated channel; the rest of the descriptor information isassembled in a register (as shown in FIG. 5D) for subsequenttransmission to the LCP 20₀₀. Once the information is assembled in this"descriptor information register" and the addresses are stored, then thecontents of the first register are shifted to a second identicalregister. In this manner, the first register can be cleared and theInitiation Module 10_(ta) is thereby freed to accept a seconddescriptor.

The information contained in the IOT descriptor register of FIG. 5Dconsists of a number of items:

(a) LCP OP CODE: these are four mutually exclusive bits, which aretranslated by the IOT from the I/O Descriptor OP code; they indicate tothe LCP the type of operation that is to be commenced.

(b) LCP Variants : these are three digits which are used to passsupplementary information to the LCP concerning the operation that is tobe commenced.

(c) IOT Digit: this digit specifies if data transfers are to beinhibited and whether or not data is to be translated.

(d) Backwards Flag: when on, this flag bit indicates that a reverseoperation is to occur.

(e) LCP Address: this is decoded from the "BF" (channel number) of theprocessor Initiate I/O instruction; this field contains three bits whichspecify one of the eight LCP Base Modules, and the other three bitswhich are used in combination to select a particular LCP in thedesignated Base Module.

(f) C Address: this is a six-digit C-Address field (file address) of theI/O Descriptor.

The combination of the IOT digit, the backwards flag, and the LCPaddress constitute the Descriptor Link (D/L) which is used by the LCP tore-establish connection to the System following a previousdisconnection. When the Processor signals the IOT that the entire I/ODescriptor has been sent, the IOT disconnects from the Processor, andthe Initiation Module 10_(ta) passes control to the Connection Module10_(tb).

Connection Module:

The Connection Module 10_(tb) of FIG. 5C has the purpose of establishinga communication path between a designated LCP, such as LCP 20₀₀, and theInput-Output Translator 10_(t). The Connection Module 10_(tb) decodesthe channel number which appears in the Processor Initiate Instruction,and, with the decoded value, selects a communication path to the LCPBase Module such as 20₀, FIG. 1A, in which the desired LCP is located.The Connection Module 10_(tb) then sends the LCP address to the selectedLCP Base Module, and then signals the Base Module, such as 20₀, to begina "Poll Test".

Poll Test

The "Poll Test" is an algorithm used by the LCP Base Module to establishconnection between the Base Module and a particular LCP; the Poll Testalgorithm is a connection which is installed by the IOT (as contrastedwith an algorithm called "poll request" which is a connection initiatedby the LCP). Once the connection between the LCP Base Module and thespecific LCP is established, the Base Module, such as 20_(o) of FIGS. 1Aand 2, becomes transparent to data transfers between the LCP and theIOT. The "Poll Test" algorithm also checks for priority, transmissionerrors, and busy conditions, any one of which, if detected, could abortthe connection attempt.

If the connection attempt is successful, the specific LCP remainsconnected to the IOT 10_(t) until the connection is terminated by theIOT. The LCP Base Module takes no further role in the communicationsbetween the chosen LCP and the IOT.

In the course of the attempted connection, certain conditions may bedetected which will stop or abort the connection attempt, with theresult that the existing condition is reported in the IOTResult/Descriptor. The following are the types of conditions detectedand reported:

(a) The channel addressed does not contain an LCP or the LCP in thechannel is off line.

(b) The LCP in the particular channel addressed is "busy", (that is, theLCP status is not 2 or 3; the use of "status counts" will be describedhereinafter).

(c) The port is busy, that is, some other LCP in that Base Module ispresently connected to the System 10.

(d) The LCP address has in it a parity error.

When the IOT and Base Module Distribution Control means uses the "PollTest" for connection to a particular LCP, then if the Poll Test resultsin electrical "connection" to that LCP, the IOT 10_(t) will transmit theDescriptor Link (D/L), the LCP OP code and variants, and the C addressto the LCP selected. After receiving this information, the LCP signalsthe IOT 10_(t) that it is either going to disconnect, or that it is nowprepared to begin to transfer data. Typically, a "Write" operation (datafrom Main Memory 10_(m) to the peripheral device, such as peripheral 50)causes the LCP selected to request a "data transfer"; on the other handa "Read" operation typically results in a disconnection.

If a "data" is requested, the Connection Module 10_(tb) passes controlover to the Data Transfer Module 10_(tc). If the LCP 20₀₀"disconnected", then communication between the LCP 20₀₀ and the IOT10_(t) is terminated until the LCP requests a re-establishment ofcommunication via the Reconnection Module 10_(td).

Data Transfer Module

In FIG. 5C the Data Transfer Module 10_(tc) is used by the IOT 10_(t) tocontrol and to direct the flow of data between a connected LCP 20₀₀ andthe Main Memory 10_(m). The LCP may be in a connected state as a directresult of the actions of the Connection Module 10_(tb), or as a resultof the actions of the Reconnection Module 10_(td) ; in either case theoperation of the Data Transfer Module 10_(tc), is the same. When controlis passed over to the Data Transfer Module 10_(tc), the A and Baddresses of the descriptor are retrieved from IOT scratchpad memory10_(ps) of FIG. 3, where they had been stored by either the InitiationModule 10_(ta), or by the Data Transfer Module 10_(tc) of FIG. 5C, atthe end of a prior data transfer operation. A memory access request ismade and the A address is transferred from the IOT 10_(t) over to theProcessor memory address register 10_(pam) in the Main System 10, FIG.3.

Assuming that a "Write" operation is in progress, in FIG. 5C, the datafrom the memory location specified by the A address is bussed bia B_(m)to the IOT Data Transfer Module 10_(tc). Once in the module, the data istranslated (if specified by the descriptor), and used to generatelongitudinal parity, and then is gated via bus B_(g) to the selected LCPsuch as LCP 20₀₀, accompanied by a strobe pulse. When the LCP 20₀₀receives the data, it acknowledges the reception by returning a strobepulse back to the IOT 10_(t).

While the data transfer from Memory 10_(m) over to the LCP 20₀₀ isoccurring, the IOT 10_(t) increments the A address and compares it tothe B address. As long as the A address is less than the B address, thereception of the acknowledged strobe pulse from the LCP 20₀₀ will causeanother memory access to be requested and will allow the data transfersequence to continue.

When the LCP buffer, such as 25₀₀, FIG. 2, is filled with data from theMemory 10_(m), the LCP signals the IOT 10_(t) that it is going todisconnect; the IOT 10_(t) then restores the incremented A address tothe IOT scratchpad memory 10_(ps), FIG. 3, and FIG. 5C-2, after which itterminates the connection between the IOT and the LCP. The LCP, such asLCP 20₀₀, then begins data transmission via B_(p) with its peripheraldevice 50; the IOT 10_(t) is now free to establish connection to anotherLCP.

Upon transferring the contents of its data buffer 25₀₀ to the peripheraldevice 50, the LCP 20₀₀ requests a re-establishment of the data path toMain Memory 10_(m). This re-establishment is handled by the LCP BaseModule 20₀ and the I0T Reconnection Module 10_(td).

In order to increase the overall rate of input-output (I/O) activity,the I0T 10_(t) may contain, as an option, an IOT Multiplexor. Thismultiplexor would enable the I0T to service an LCP during those memorycycles which would otherwise be lost while the I0T was busy with somenon-memory function.

Reconnection Module

An LCP, such as 20₀₀, after having been connected to the I0T 10_(t) andreceiving the Command Descriptor (C/D) and the Descriptor Link (D/L),then the LCP 20₀₀ may disconnect from the system in order to communicatewith its associated peripheral device, such as device 50. Now, if thatLCP subsequently requires access to Memory 10_(m), it sends a request tothe Base Module 20₀. An algorithm called the "Poll Request" is themethod by which the LCP Base Module (in response to the request of theLCP) attempts to connect the LCP back to the IOT 10_(t). The Base ModuleDistribution Card contains hard wired logic to accomplish this. Thepurpose of the Reconnection Module 10_(td) is to acknowledge the "PollRequest" and to re-establish a data path over to the IOT 10_(t).

The Reconnection Module 10_(td), during the reconnection attempt, andworking with the Base Module, as 20₀, resolves any priority conflictsthat may arise between various requesting LCP's. When priority isresolved, the Reconnection Module establishes the data path from therequesting LCP over to the Main Memory 10_(m).

Once the data path is re-established, the LCP returns the DescriptorLink over to the IOT 10_(t). (The Descriptor Link was originally passedto the LCP 20₀₀ during the original connection sequence). The BaseModule 20₀ takes no further role in the LCP-IOT communication. Followingthe transfer of the Descriptor Link, the Reconnection Module 10_(td)passes control to the Data Transfer Module 10_(tc).

The IOT 10_(t) must have the ability to accept, store and to modify datafield addresses in order to transfer data to and from the correct memorylocations. Because Main Memory 10_(m) may include up to two-milliondigits (addresses 0 to 1,999,999), and because the various input-outputdevices may address the Memory 10_(m) directly, then the I/O descriptordata field addresses must be seven digits long. An I/O descriptor datafield address must be either MOD 2 or MOD 4 (modulus is abbreviated toMOD); no odd addresses are permitted. Because odd addresses are notallowed, the least significant bit of the least significant digit is notrequired. Furthermore, since the most significant digit can be only a"1" or a "0", only one bit is required for the digit position. Withthese facts, it is possible to construct a seven digit address using 24bits. The format for the I/O descriptor data field address is shown inthe table V below.

                  TABLE V                                                         ______________________________________                                         ##STR5##                                                                     ______________________________________                                         I/O Descriptor Data Field Address                                             Note:                                                                         ##STR6##                                                                 

In the address, the digit G may be a one or a zero, digits B through Fmay be any decimal value (0 through 9), and digit A may be any evendecimal value (0 through 8).

As was indicated in FIG. 3, the IOT 10_(t) has a scratchpad memory 10.This is shown in greater detail in FIG. 5F. The IOT contains 256 wordsof scratchpad memory, each word of which is 24 bits long. As seen inFIG. 5F, the scratchpad memory is divided into five major areas. Theareas marked A and B are used to store the begin (A) and the end (B)addresses of the memory data field; both of these addresses are 24 bitslong. The areas marked EXRDW 1 and EXRDW 2 are used to store extendedresult descriptors wherein each of these words are 16 bits long. Thearea marked "temporary storage" is used to store flags indicative oferrors detected during IOT operation. When the Result Descriptor isassembled, the information from the temporary storage area is added toany existing Result Descriptor information. Each of the five major areasis subdivided into 64 individual locations, one for each channel.

The scratchpad locations are addressed by a combination of eight bitswhich represent the Base Module number and the LCP number, the endaddress flag (ADDRESB), and the extended result descriptor flag (EXRDW1). The six least significant bits of the scratchpad address (BaseModule number and LCP number) are derived from the BF portion of theProcessor's Initiate Instruction (BFA=base number, BFB=LCP number). TheEXRDW 1 signal is generated by the IOT 10_(t) whenever access isrequired to either the extended Result Descriptor word, or to thetemporary storage area. ADDRESB is generated by the IOT whenever accessis required to a B address or to the second extended Result Descriptorarea.

The memory elements of the scratchpad 10_(ps) consist of 24 RAMS(256×1), organized in a 64×4×24 array (64 channels, 4 words per channel,24 bits per word). As seen in FIG. 5G, the eight-bit address bus,B_(ad), goes to all RAMS, 60₀, 60₁ . . . 60₂₄, in the array, as does theWrite Enable line 68. Each RAM has one data input line and one dataoutput line; these individual data lines are combined to make up thedata input (RAMIN) 70₁ and the data output (RAMOUT) 70₀ bussesrespectively.

When the scratchpad address is applied to the array, and the "WriteEnable" is made active, the data on the IOT address bus is written intothe RAMS. In order to read from the scratchpad, the desired locationmust be specified with the scratchpad address and the "read enable" mustbe made active. The requested data is then transferred from thescratchpad to the IOT address bus.

Address Store:

During the execution of an Initiate I/O Instruction, the Processor10_(p) assembles the beginning (A) and the ending (B) addresses of thedata field. The Processor then transfers the complete A address from theProcessor register 10_(pr) to the IOT address bus. At the proper pointof the IOT initiation sequence, the IOT generates the appropriatesignals, then gates the Base Module and the LCP address bits to thescratchpad 10_(ps). Now, with the channel's scratchpad locationaddressed and with the "Write Enable" active, the A address can bewritten into the scratchpad. Subsequently the Processor 10_(p) placesthe end (B) address on to the IOT address bus and again the IOTgenerates the proper control signals along with the Base Module and LCPaddress. This time, however, the IOT also generates ADDRESB, thuscausing the address on the bus to be written into the B address area ofthe scratchpad (FIG. 5F). The beginning and ending addresses of the datafield have now been stored in the channel's address memory scratchpad10_(ps). When the data transfer operation begins, these scratchpadlocations will be accessed by the Data Transfer Module 10_(tc) (FIG.5C).

Input/Output Translator: Detailed Description

The following sections will describe in detail the elements andoperating functions of the Input/Output Translator as follows:

I. Glossary of terms and signals.

II. Description of hardware and elements of FIGS. 5C-1 through 5C-29.

III. Description of operations and functions of Input/Output Translator

I. The attached glossary of terms and signals will define the acronymsused in the detailed drawings of the Input/Output Translator and willalso define and describe their basic functions. Hereinafter, generally,the acronyms will be used without further detailed explanation except incertain instances where a newly introduced acronym is used.

    __________________________________________________________________________    GLOSSARY (INPUT/OUTPUT TRANSLATOR)                                            Term     Definition and Function                                              __________________________________________________________________________    AASCII   A OP Buffer ASCII Flag. Indicates that the                                    descriptor in the A OP buffer requires ASCII                                  translation.                                                         ABASEn   Base Address Bit (n = 1,2, or 4). These three bits                            specify the base to which the descriptor in the                               A OP buffer is directed                                              ACCNCLF  Conditional Cancel Flip-flop. Indicates that a                                Conditional Cancel descriptor is in the A OP                                  buffer.                                                              ACVALDF  C Address Valid Flip-flop. Indicates that the                                 descriptor in the A OP buffer contains a C                                    address.                                                             ADxn     Address Bus (x = A thru G, n = 1,2,4, or 8).                                  The ADxn bus is bidirectional between the                                     processor and the IOT. Within the IOT, ADxn is                                the path between the address register and the                                 address memory scratchpad. Refer to FIG. 5C-2                                 for a representation of ADxn functions.                              ADCM = n Address Compare = n. ADCM = n is generated by the                             subtraction of CMR from the address register.                                 The value of n is the absolute difference between                             the two registers, and represents the amount                                  (in digits) remaining in the data field.                             ADDERF   Address Error Flip-flop. Indicates that the IOT                               has incorrectly incremented the data-field                                    address during the data transfer.                                    ADDRESB  B Address. ADDRESSB is used as the MSD of the                                 IOT scratchpad address. When true, ADDRESSB                                   causes the second half of the scratchpad to be                                accessed. See FIG. 5F.                                               ADMOD2   Address is Mod 2. When true, ADMOD2 indicates                                 that the address in the address register is mod 2.                   ADDR     IOT Address Register, FIG. 5C-2.                                     ADRxn    Address Register Output Bus (x = A thru G, n =                                1,2,4, or 8). ADRxn is the input to the CMR                                   register and is also used as one of the inputs                                to the address adder. See FIG. 5C-2.                                 ADSLn    Address Select n (n = 0 thru 7). Address Select                               for base number n. See ADSELF.                                       ADSELF   Address Select. Address Select is a signal which                              is sent to a base during poll test. If the poll                               test is successful and the connection is made,                                Address Select remains true for the duration of                               the connection.                                                      AECHO    A OP Buffer Echo OP Flag. Indicates that the A                                OP buffer contains an Echo descriptor.                               AEXRDF   A OP Buffer Extended Result Descriptor Flag.                                  Indicates that the A OP buffer contains an                                    Extended R/D descriptor                                              AFULF    A OP Buffer Full Flip-flop. Indicates that the                                A OP buffer contains a complete descriptor.                          AGLINHF  Access Granted Level Inhibit Flip-flop. Indicates                             that no other devices will be granted access to                               memory during the course of an Initiate I/O.                         ALNINE   All Nines. ALNINE is a result of the ADDR-CMR                                 subtraction; when the six most significant                                    digits of the result are all nines, the least                                 significant digit (LSD) contains the complement                               of the difference (in digits) between the A and                               the B addresses.                                                     ALZER    All Zeros. ALZER is a result of the ADDR-CMR                                  substraction; when the six most significant                                   digits of the result are all zeros, the LSD                                   contains the difference (in digits) between the                               A and the B addresses.                                               AR-CMR   Address Register Minus Compare Register. AR-CMR                               causes the contents of CMR to be substracted from                             the contents of ADDR. The result is the amount                                of memory remaining in the data field. (See                                   FIG. 5C-2).                                                          AREAD    A OP Buffer Read Descriptor Flag. Indicates                                   that the A OP buffer containns a Read descriptor.                    AS-EB    ASCII-EBCDIC Translate. AS-EB activates the IOT                               translator; if a read is in progress, the data is                             translated from ASCII to EBCDIC, and if a write                               is in progress, the data is translated from                                   EBCDIC to ASCII.                                                     ATEST    A OP Buffer Test Descriptor Flag. Indicates                                   that the A OP buffer contains a Test descriptor.                     AUCNCLF  A OP Buffer Unconditional Cancel Flip-flop.                                   Indicates that the OP buffer contains an                                      Unconditional Cancel descriptor.                                     AWRITE   A OP Buffer Write Descriptor Flag. Indicates                                  that the A OP buffer contains a Write descriptor.                    BnHGH    When true, BnHGH indicates that the base module                               connected to the bottom half of driver card n                                 (n = 1,2,3, or 4) has presented a higher global                               priority than the base connected to the top half.                    BACKOP   Backwards Operation Flag. When true, BACKOP                                   indicates that the operation in progress is a                                 backward operation.                                                  BADRS    B Address. BADRS is the term used in the IOT                                  scratchpad to address the second half of the                                  scratchpad. (See FIG. 5F).                                           BASEnP   BASE n PRESENT (n = 0 thru 7). When true,                                     BASEnP indicates that the specified base is                                   present in the system.                                               BCCNCLF  B OP Buffer Conditional Cancel Flip-flop. When                                set, BCCNCLF indicates that the B OP buffer                                   contains a Conditional Cancel descriptor.                            BECHO    B OP Buffer Echo OP Flag. Indicates that the                                  B OP buffer contains an Echo descriptor.                             BENB     B Enable. When true, BENB enables data bus B                                  onto the base driver card, BENB is derived from                               the ENBCHn terms, FIG. 5C-8, which specify both                               the driver card and the data bus to which the                                 driver card is to be connected.                                      BEXRDF   B OP Buffer Extended R/D Flip-flop. See AEXRDF.                      BF       B OP Buffer Descriptor Flip-flop. When set, BF                                indicates that the descriptor to be executed is                               to be taken from the B OP buffer.                                    BF       B Field Variant. BF is that portion of the                                    Initiate instruction which specifies the channel                              number of the device which is to be initiated.                                The MSD (most significant digit); BFA, specifies                              the base containing the LCP, and the LSD, BFB,                                specifies the address of the LCP within the                                   specified base.                                                      BFULF    B OP Buffer Full Flip-flop. When set, BFULF                                   indicates that a complete descriptor is in the                                B OP buffer.                                                         BLCPn    B OP Buffer LCP Address Bit n (n = 1,2, or 4).                                These three bits, derived from the BFB portion of                             the Initiate instruction, specify the address of                              the LCP within the addressed base.                                   BREAD    B OP Buffer Read Descriptor Flag. When true,                                  BREAD indicates that the B OP buffer contains a                               Read descriptor.                                                     BSEL     Bus Select. When true, BSEL enables the selection                             of a data path thru the IOT. See FIGS. 5C-6 and                               5C-7.                                                                BTEST    B OP Buffer Test Descriptor Flag. When true,                                  BTEST indicates that the B OP buffer contains a                               Test descriptor.                                                     BUCNCLF  B OP Buffer Conditional Cancel Flag. See AUCNCLF.                    BUFFULF  Both Buffers Full Flip-flop. When set, BUFFULF                                indicates that both the A and the B buffers are                               full and that the IOT cannot accept another                                   descriptor.                                                          BWRITE   B OP Buffer Write Descriptor Flag. When true,                                 BWRITE indicates that the B OP buffer contains a                              Write descriptor.                                                    CCLUCL   Conditional/Unconditional Cancel Flag. When true,                             CCLUCL indicates that either a Conditional or an                              Unconditional Cancel descriptor is being executed.                   CCNCLF   Conditional Cancel Flip-flop. When set, CCNCLF                                indicates that a Conditional Cancel descriptor is                             being executed.                                                      CEN      C Enables. CEN enables the C address of the                                   descriptor from the selected OP buffer onto the                               IIO bus (see FIG. 5C-19).                                            CHNAF    Data Channel A Busy Flip-flop. When set, CHNAF                                indicates that the connection module, the reconnection                        module, or one of the data transfer modules is                                using data bus A (see FIG. 5C-7).                                    CHNBF    Data Channel B Busy Flip-flop. When set, CHNBF                                indicates that the connection module, the reconnection                        module, or one of the data transfer modules is using                          data bus B (see FIG. 5C-7).                                          CHNSELF  Channel Select Flip-flop. Channel Select is a                                 signal which is sent to a distribution card to                                signal the start of a poll test operation.                           CHSELn   Channel Select n (n = 1 thru 4). CHSEL is the - designation for               the Channel Select signal sent                                                to the designated base.                                              CH8      Channel Eight. When true, CH8 indicates that a                                descriptor has been issued for the IOT (the IOT                               is always designated as channel 8).                                  CMR      Compare Register. The Compare register is used                                to hold the subtrahend of the ADR-CMR subtraction.                   CNnn     Connection Module Sequence Count nn (nn = 00 thru                             08).                                                                 CNAF     Connection Module to Data Bus A Connection Flag.                              When set, CNAF indicates that the connection                                  module is connected to data bus A.                                   CNASL    Connection Module Address Select Level. CNASL is                              the signal from the connection module which                                   causes the Channel Select signal to be sent                                   during the connection sequence.                                      CNBF     Connection Module to Data Bus B Connection Flip-                              flop. When set, CNBF indicates that the                                       connection module is connected to data bus B.                        CNDTnST  Connection Module Data Transfer Module n Start                                Level (n = 1 or 2), CNDTST is generated at CN08,                              FIG. 5C-18, time if the descriptor specifies                                  that a data transfer is to occur immediately                                  following the connection.                                            CNENCHn  Connection Module Enable Channel n (n = 1 thru 4).                            CNENCHn generates ENBCHAn or ENBCHBn, which                                   connects driver card n to either data bus A or - data bus B                   (FIG. 5C-1). CNENCHn also                                                     generates CHSELn (see FIGS. 5C-6 and 5C-8).                          CNENTO   Connection Module Enable Timeout Level. When - true, CNENTO                   starts the connection module timer;                                           if more than 64 microseconds elapse between the                               transmission of ST10F and the reception of LCPSTF,                            the timer times out and the Timeout flip-flop is                              set.                                                                 CNGLPWF  Connection Module Gate LPW Flip-flop. When set,                               CNGLPWF causes the accumulated LPW to be                                      transmitted to the distribution card.                                CNLCP    Connection Module LCPSTF. CNLCP is LCPSTF as                                  controlled by the connection module (see LCPSTF).                    CNLCP<<0 Connection Module Clear LCPSTF signal.                               CNLPW<<0 Connection Module Complement LPW (see LPW<<C).                       CNLPW<<1 Connection Module Initialize LPW (see LPW<<1).                       CNRCSL   Connection Module Reconnection Module Start Level.                   CNSIO    Connection Module STIOP (see STIOF).                                 CRDnBY   Driver Card n Busy (n = 1 thru 4). -CRDPRTn Driver Card n                     Present (n = 1 thru 4).                                              CVALID   C Address Valid. When true, CVALID indicates                                  that the descriptor being received contains a                                 C address.                                                           DAxn     Data Bus A Digit x Bit n (x =  A thru D, n =                                  1,2,4, or 8). Data Bus A is one of the two                                    paths between the data transfer modules and the                               base driver cards (see FIG. 5C-1).                                   DBxn     Data Bus B, Digit x Bit n (x = A thru D, n =                                  1,2,4,or 8). Data Bus B is one of the two paths                               between the data transfer modules and the base                                driver cards (see FIG. 5C-1).                                        DLB<<DL  Transfer Descriptor Link to Descriptor Link Bus.                              DLB<<DL transfers the descriptor link from the                                selected OP buffer to the Descriptor Link bus                                 during the connection sequence.                                      DLBxn    Descriptor Link Bus digit x, bit n (x = A thru D,                             n = 1,2,4, or 8).                                                    DLR<<DAT Transfer Data Bus to Descriptor Link Register.                                When true, DLR<<DAT transfers the data from the - specified data              bus into the Descriptor Link                                                  register (see FIG. 5C-2).                                            DTn      Data Transfer Module n (n = 1 or 2).                                 DTnAF    Data Transfer Module n to Data Bus A Connection                               Flip-flop (n = 1 or 2). When set, DTnAF indicates                             that the specified data transfer module is                                    connected.                                                           DTnENTO  Data Transfer Module n Enable Timer Level (n = 1                              or 2). When true, DTnENTO starts a 64 microsecond                             timer at STIOF time. If the LCP does not respond                              with LCPSTF before the timer times out, the - timeout flip-flop               is set and a result descriptor                                                is stored, reporting the error.                                      DTnGLPW  Data Transfer Module n Gate LPW (see GLPW).                          DTnRCVxO Data Transfer Module n Receive from Data Bus x                                (n = 1 or 2, x = A or B). The DTnRCVxO terms                                  control the data path switching between the                                   data transfer modules and the data busses for                                 read operations (see FIG. 5C-11).                                    DTMPEF   Data Transfer Module Memory Parity Error Flip-                                flop. When set, DTMPEF indicates that a memory                                parity error has been detected.                                      EB<<AS   Translate ASCII to EBCDIC. If the translate                                   bit is set in the IOT digit of a read descriptor,                             EB<<AS is generated to enable the translator                                  during the data transfer sequence.                                   ECHO     Echo is a descriptor which causes the specified                               LCP to read data from memory, and then return                                 that same data to the same area of memory.                           EMOD2F   End Address Mod 2 Flip-flop. When set, EMOD2F                                 indicates that the ending address of the descriptor                           is mod 2.                                                            ENBCHxn  Enable Data Bus x to Driver Card n (x = A or B,                               n = 1 thru 4). The ENBCHxn terms are used during                              the connection sequence to connect one of the data                            bussses to the selected driver card.                                 EXRDF    Extended Result Descriptor Flip-flo. When set,                                EXRDF indicates that the LCP is storing an                                    extended result descriptor.                                          EXRDWI   Extended Result Descriptor Word 1. EXRDW1 is                                  used as address bit 64 of the IOT scratchpad                                  memory, and as such, specifies those locations                                into which the extended result descriptor words                               are written. See FIG. 5F.                                            FRCBP    Force Bad Parity. If a memory parity error is                                 detected, DTMPEE is set and FRCBP is generated.                               FRCBP then causes the parity error to be passed                               on to the LCP, which then makes the decision as                               to how the error is to be handled.                                   GLPWF    Gate Longitudinal Parity Word Flip-flop. When                                 set, GLPWF causes the accumulated LPW to be                                   transmitted to the LCP.                                              GOF      GOF is a substrate counter whose function is to                               flag various conditions that may occur within                                 a logic state. The conditions flagged vary                                    from state to state.                                                 GOFF     GOFF is a substrate counter (see GOF).                               GP       Global Priority. Global priority is the means                                 by which the IOT determines which of several                                  possible requesting LCPs is to be granted access                              to memory.                                                           IIOxn    Initiate I/O bus digit x, bit n (x = A thru D,                                n = 1,2,4, or 8). The IIO bus transfer                                        descriptor information from the OP buffer to the                              specified data bus.                                                  ILSTCF   Illegal Status Flip-flop. When set, ILSTCF                                    indicates that the IOT found the LCP to be in                                 an incorrect status for the operation in progress.                   INR      Information Register. The IN register is a four-                              digit register whose function it is to accept                                 read data from memory for subsequent transfer                                 to the LCP. The IN register also accepts                                      information generated within the IOT and transfers                            that information to memory (see FIG. 5C-13).                         INF      IN (Register) Full Flip-flop. When set, INF                                   indicates that the IN register has received data.                    INTJ     Set Processor Interrupt. When true, INTJ indicates                            that an I/O operation has been completed and that                             processor attention is required.                                     INTREQ   Interrupt Request. When truw, INTREQ indicates                                that a LCP requires access to memory and has                                  sent its global priority level to the IOT.                           IOCBF    I/O Compare Bus Flip-flop. When set, IOCBF                                    indicates that the descriptor data field addresses                            are equal, or nearly so.                                             IOCPTM   I/O Clock Pulse Time. When true (MTCF/ * QTCF),                               IOCPTM allows one I/O clock pulse to go to the - IOT.                IOTADL   IOT Address Load. When true, IOTADL enables                                   the loading of the descriptor address into the                                IOT address memory scratchpad (FIG. 5C-2).                           LPW      Longitudinal Parity Word. The LPW is a means of                               checking the validity of information transferred                              between the IOT and the connected LCP. The LPW                                is generated in the transmitting device by                                    treating each word transferred as a 16-bit                                    number and performing the binary addition (without                            carry) of each word in the transmission. The final                            sum of the additions is transmitted to the                                    receiving device at the end of the operation;                                 that sum is then added to a sum generated in a                                similar manner in the receiving device. If no                                 errors are detected in the transmission, the                                  addition of the two sums will yield a zero                                    result. If an error had occurred, the addition                                would yield a non-zero sum.                                          LPW<<C   Complement LPW. When true, LPW<<C causes the                                  word being transmitted to be added to the LPW                                 sum being accumulated.                                               LPW<<1   Initialize LPW. At the start of an information                                transfer, the LPW is initialized by forcing all                               bits in the LPW register to 1.                                       MAGF     Memory Access Granted Flip-flop.                                     MARF     Memory Access Request Flip-flop.                                     OTB      Output Buffer. The OTB is that portion of the IOT                             whose function it is to establish data paths thru                             the IOT and to handle all data transfers within                               the IOT (see FIG. 5C-1).                                             OTB = O/ OTB Not Equal to Zero. Used at result descriptor                              time, OTB = O/ indicates that some error condition                            exists (the result descriptor is in the OTB                                   register when this signal is active).                                OTBR     Output Buffer Register. The OTBR is a four-                                   digit register in the data transfer module                                    (see FIG. 5C-13).                                                    OTBF     Output Buffer (Register) Full Flip-flop.                             OURCH    Our Channel. When true, OURCH indicates that the                              IOT has detected that the IIO instruction in                                  progress is for a base and LCP and that the IOT                               must store the IIO information.                                      RAMIN    RAM Input. RAMIN is the data input to the                                     address memory RAM chips.                                            RAMOUT   RAMOUT is the output bus from the address memory                              RAM chips. (See FIG. 5G).                                            RCnn     Reconnect Module Sequence Count nn.                                  RCADSL   Reconnect Module Address Select Level. See                                    Address Select.                                                      RCAF     Reconnect Module to Data Bus A Connection Flip-                               flop. When set, RCAF indicates that the reconnect                             module is connected to data bus A.                                   RCBF     Reconnect Module to Data Bus B Connection Flip-                               flop. When set, RCBF indicates that the reconnect                             module is connected to data bus B.                                   RCDTSL   Reconnect Module Data Transfer Module Start level.                            When true, RCDTSL indicates that the reconnection                             sequence is complete, and passes control to the                               data transfer module.                                                RCENCHn  Reconnect Module Enable Channel n (n = 1,2,3,                                 or 4). When true, RCENCHn generates the data                                  bus to driver card enable signals (ENBCHxn)                                   and the Channel Select levels required to estabish                            a data path within the IOT (see FIG. 5C-8).                          RCENTO   Reconnect Module Enable Timeout Level.                               RCLPW    Reconnect Module LPW. See LPW.                                       RCLPW<<C Reconnect Module Complement LPW. See LPW.                            RCLPW<<1 Initialize Reconnect Module LPW. See LPW<<1.                         REG      Auxiliary Register. REG is a two-digit register                               in the data transfer module which is used for                                 character shifting in mod 2 operations. See FIGS.                             5C-13, 5C-22, 5C-23.                                                 STC = nn LCP Status Count = nn (nn = 0 thru 15). The LCP                               status counts are used by the LCP to inform the                               IOT of the action the LCP is currently executing,                             and to inform the IOT of the action it is to                                  take in response to the LCP's actions.                               STIOF    Strobe I/O Flip-flop. The Strobe I/O flip-flop                                is used by the IOT to signal the LCP or the                                   distribution card that a transfer of information                              has occurred. Upon receipt of the information,                                the LCP responds with LCPSTF and status                              TnHGH    When true, TnHGH indicates that the top half of                               driver card n (n = 1,2,3, or 4) has received a                                higher global priority than has the bottom half.                     TIMOUTF  Timeout Flip-flop. At the time the IOT sets                                   STIOF, it also starts a 64 microsecond timer.                                 When LCPSTF is received, the timer is reset.                                  IF LCPSTF is not received before the timer times                              out, TIMOUTF is set, and an IOT TIMEOUT result                                description is written.                                              VPERRF   Vertical Parity Error Flip-flop. When set,                                    VPERRF indicates that a parity error was                                      detected on a word transfer from the LCP.                            ZnnnGDxx GROUND. Ground potential.                                            ZnnnM2xx Minus 2 volts.                                                       ZnnnP5xx Plus 5 Volts                                                         __________________________________________________________________________

II. cl DESCRIPTION OF HARDWARE AND ELEMENTS OF INPUT-OUTPUT TRANSLATOR

In FIGS. 5C-1, 5C-1a there is seen an overall block diagram showing therelationship of the Input-Output Translator Module to the rest of thesystem.

The Main Processor 10_(p) provides input-output descriptors to theInitiation Module 10_(ta) which then activates the Connection Module10_(tb) and the Data Transfer Modules 10_(tc). The first and second DataTransfer Modules 10_(tc) connect to Main Memory 10_(m) by means ofmemory write bus B_(10W) (MWB) and and memory read bus B_(10R) (MRB).The above-mentioned IOT modules and the Reconnection Module 10_(td)operate through an output buffer 10_(OTB) to connect to either data busA, D_(A) or to data bus B, D_(B). The data busses connect to four basedrivers 10_(d1), 10_(d2), 10_(d3) and 10_(d4). These drivers each handletwo Base Modules so that the four drivers handle Base Modules 20₀ -20₇.

FIG. 5C-2 shows the elements involved in addressing of the Input-OutputTranslator 10_(t). A multiplexor 63 receives memory address and othercontrol signals which are transmitted to the IOT address register 60,which transmits to a dual buffer driver M20_(e) and also to a comparisonregister 61, thence to a dual buffer S05 and over to Adder 62. The IOTaddress register 60, the comparison register 61 and the adder 62 are inthe Data Transfer Module 10_(tc). Also providing input to themultiplexor 63 is the processor address register 10_(pr). Register10_(pr) also provides signals to memory address register 10_(pam).

Data busses A (DAxn) and B (DBxn) connect to multiplexor 64 whichtransmits signals to a quad J-K flip-flop M11 which connects to dualquad buffer driver M20_(a) whose output is connected to multiplexor 65,thence to a register 66 which is designated as the Data-Link Register(DLR). The output of the Data-Link Register is connected to bufferdrivers M20_(c) and M20_(b) whose output is connected to the RAMscratchpad memory 10_(ps). The scratchpad addresses from the Processor10_(p) are also fed to the IOT scratchpad memory 10_(ps). The addressbus AD_(xn) . . . O conveys its signals to a level changer 67. Theoutput of IOT scratchpad memory 10_(ps) is connected to another levelchanger 68 which connects to buffer driver M20_(d). The references B/Cand C/B on the level changers 67, 68 refer to BCML or Burroughs CurrentMode Logic (B) and the C refers to CTL or Complementary TransistorLogic.

Thus, in order to transfer data to and from the correct memorylocations, the IOT must have the ability to accept, store, modify datafield addresses. This is implemented by the elements shown in FIG. 5C-2.

FIG. 5C-3 shows the elements involved in transferring the descriptorlink from the OP buffers M11_(a) and P14 on to the descriptor link bus(DLB). The descriptor link in FIG. 5C-3 comes from the main system onthe Read Bus into the B and the A OP buffers, M11_(a) and P14; it isthen passed through the quad 4-1 multiplexor M01_(a) and thence to dualquad buffer drivers M20_(f), M20_(g), and M20_(h), which have outputswhich form the II0 bus (initiate input-output) and the Descriptor LinkBus.

The Descriptor Link Register (DLR) 66 of FIG. 5C-2 is shown in moredetail in FIG. 5C-4. The input and control signals enter a series ofquad 4-1 multiplexors M01_(b), M01_(c), M01_(d). The outputs of thesemultiplexors are then fed to a series of four quad JK-D flip-flopsM11_(b), M11_(c), M11_(d), M11_(e). The outputs of the last twoflip-flops are then fed to a group of dual quad buffer drivers M20_(i),M20_(j), M20_(k) and M20₁. Thus, there has been enabled the loading ofthe descriptor link from the bus into the descriptor link register 66 ofFIG. 5C-4.

FIG. 5C-5 shows the elements involved in storing the descriptor linkword into a temporary holding register. The memory bus MBUS and the databusses A and B input to a quad 4-1 multiplexor M01_(e), which feeds itsoutput to a quad JK-D flip-flop M11_(f) ; the output of M11_(f) is fedto a dual quad buffer driver M20_(m), whose output forms the descriptorlink bus, DLBxn. The JK-D flip-flop M11_(f) is gated by a signal LDDLRA(Load Descriptor Link Register A) which signal derives from controlsignals from dual quint buffer S05_(a), hex 2 input AND gate S06_(b),and AND gate S06_(a). Flip-flop outputs from the Reconnection Module todata bus A and data bus B are shown as input signals RCAF, RCBF.

FIG. 5C-6 shows the Connection Module where the terms A BASEn or B BASEnterms are used as input selects for a pair of multiplexors, M01_(f) andM01_(g). The input to these multiplexors are the "busy" levels from thefour base driver cards 10_(d1), 10_(d2), 10_(d3), 10_(d4) (FIG. 5C-1).The input signals to the quad 4-1 multiplexors M01_(f), M01_(g) are thedriver card n busy signals which have a "/" mark to signify that thesignal is "false". The outputs of the multiplexors are fed to hex2-input and AND gate S06_(c), thence to a quad input AND-OR gate S02_(a); also to multiplexor M01_(h) which has outputs going to a dual1-out-of-8 Decoder M08_(a), which then provides connection module"enable" channel signals. Dual 3-input AND gate S07_(a) provides the busselect signal, BSEL.

FIG. 5C-7 shows the Connection Module in its selection of a bus wherethe bus select signal BSEL goes to what is called the output buffercommunications card (OTB-COM). Flip-flop signals from the first andsecond Data Transfer Modules on the A bus and B bus come into dual ORgates S09_(a), S09_(b). The OR gate outputs go to the 2-input AND gatesS06_(d), S06_(e) and thence to AND gates S06_(f) and S06_(g). Theoutputs of these AND gates are then fed to JK-D flip-flops M11_(g),M11_(h), and the other outputs are fed to Exclusive-OR gates S08_(a),S08_(b). The outputs of the JK-D flip-flops M11_(g), M11_(h) are fed tobuffers S05_(c) and S05_(d) to provide further control output signals indeveloping the connection sequence.

The enable logic for the driver card busses is shown in FIG. 5C-8. Theinput signals for the Connection Module enable channel and theReconnection Module enable channel are fed to quad 4-1 multiplexorsM01_(h) and M01_(i). The outputs of these multiplexors are then fed toJK-D flip-flops M11_(i) and M11_(j) and part of their outputs formchannel enable signals while other parts of their outputs are fed tomultiplexor M01_(j) and thence to hex 2-input AND gates S06_(h),S06_(i), S06_(j), S06_(k) to provide channel select signals.

FIG. 5C-9 shows the terms or signals to provide the control required toestablish the data paths between the various modules and buses. Thus,there are generated the "select terms" to provide the control signals toestablish data paths. Signals from the Connection and ReconnectionModule and the Data Transfer Modules along buses A or B form inputs toExclusive-OR gates S08_(c), S08_(d), S08_(e), S08_(f). The outputs ofthese gates form select term signals, some of which are derived fromdual buffer S05_(e).

FIG. 5C-10 shows generation of select levels for "transmit" whereby thesignal XMITA gates the II0 bus (initiate input-output bus which containsthe descriptor and descriptor link) onto the data bus A. Likewise theXMITB signal gates the II0 bus onto data bus B. The data bus A isdesignated as DAxn and the data bus B is designated as DBxn (FIG.5C-11). Referring to FIG. 5C-10, signals from the first and second DataTransfer Modules of the Input-Output Translator Unit are fed to theAND-OR gates S02_(b) and S02_(c). The outputs of these gates are thenfed to Exclusive-OR gates S08_(g) and S08_(h) to develop the transmitselect level signals.

In FIG. 5C-11, there is shown the Output Buffer (OTB) 10_(OTB) (also seeFIG. 5C-1) as a data path switching element. The signals XMITA and XMITBgate the 110 bus onto the data buses DAnx or DBnx. The 110 bus feeds tomultiplexors M01_(k) and M01₁ ; their output is fed to buffer driversM20_(n) and M20₀. The outputs of these multiplexors are controlled bysignals from JK-D flip-flop M11_(i) and M11_(j) plus buffer drivers M20_(p), M20_(q), M20_(r) and M20_(s), in addition to buffer driversM20_(t) and M20_(u). Data is thus passed on to data buses A and B.

FIG. 5C-12 shows the module select logic in the Data Transfer Module.Signals from the Connection Module and the Reconnection Module and theData Transfer Module are fed to AND gates S06₁, S06_(m), S06_(n),S06_(o), _(p),q,r,s,t,u,v,w,x,y,z and S06_(a'),b',c',d',e', ; thus toset the connection flip-flops for a selection from the Data TransferModule to the data bus A or B.

Momentarily referring again to FIG. 5C-1, it will be noted that dataenters the specified Data Transfer Module 10_(tc) from the Main Memory10_(m) via the Read bus B_(10R) (MRB), and then passes through theOutput Buffer 10_(0TB) (which provides the data path switching logic)and from there the data goes through an enabled Driver Card to theparticular Base Module which contains a selected Line Control Processor.

In FIG. 5C-13 there is shown a detailed drawing of the Data TransferModule. Data transfers from the memory Read bus (MRB) B_(10R) are fed tothe information register multiplexors M01_(m) and M01_(n). Their outputsare then fed to the information registers (INR) M11_(k) and M11_(l).Buffers S05_(f), S05_(g), S05_(h) receive and supply the indicated dataand control signals. Multiplexors M01_(p) and M01_(q) take the output ofthe Information Registers (INR) through translators 69 and 70 ifnecessary or bypass them over to multiplexors M01_(r) and M01_(s). TheJK-D flip-flop M11_(m) is a two digit register used for charactershifting in MOD 2 operations. The outputs of the output buffermultiplexors M01_(r) and M01_(s) are fed to output buffers M11_(n) andM11_(o) and thence to buffer drivers M20_(v), M20_(w), M20_(x), andM20_(y). Data is thus transferred to the data transfer buses DT1 (AB)n .. o and also DT1(DC)n . . o.

As seen in FIG. 5C-14, the data buses D_(A), D_(B) are connected to theBase Driver Cards. The data buses A and B connect to multiplexor M01_(t)and to buffer drivers M20_(z) and M20_(z'). The output of multiplexorM01_(t) is fed to a level changer S10_(a) (Burroughs Common Mode Logic -Complementary Transistor Logic), thence through tri-state hex inverter71, 72 and thence to multiplexor 73 whose output is fed to another levelconverter S10_(b) (Complementary Transistor Logic-Burroughs Common ModeLogic). The inverters 71 and 72 gate the output of the level changers toone of two bases (top and bottom) connected to the Base Driver Card. Atthe driver card, the bases are designated as Top and Bottom. Thus, thedata lines to the Base Module are designated DIN_(xn) B/1 or T/1 (bottomof first driver or top of first driver).

FIG. 5C-15 is a flow diagram showing the sequential steps taken by theInitiation Module 10_(ta). Later discussion of exemplary operations willrefer to this flow diagram.

As will be later described, the signal LOAD BOP enables the loading ofthe base number, the LCP number and the decoded OP-code into the B OPbuffer shown in FIG. 5C-16. The B8 bit from the memory read bus (MRB) ismultiplexed into various positions within the B buffer of the InitiationModule. The B8 bit from the memory read bus is fed to multiplexorsM01_(u) and M01_(y). The B8 bit is also fed to buffer S05_(i), theoutput of which connects to the input of multiplexors M01_(w) andM01_(x) ; the outputs of these multiplexors are connected to amultiplexor M11_(p) and an 8-bit D-latch P14_(b). The output ofmultiplexor M01_(u) connects to latch P14_(a) which has an output signalthat is decoded by decoder M08_(b) to provide the ECHO-OP signal.Multiplexor M01_(v) is connected to 3 latches P14_(c), P14_(d) andP14_(e).

FIG. 5C-17 shows the OP buffer shift control. Since the B OP buffer isshifted into the A OP buffer at each clock, but because only two digitsof the B OP buffer change at any time, data is usually being shiftedfrom the B OP buffer to the A OP buffer in a series of 2-digit transfersas seen in FIG. 5C-17 when STCF (Status Count Flip-flop) and theIOCF/(Input/Output Compare Flip-flop) are "true" indicating the end ofthe descriptor; then BFULF (buffer full) is set and, at the same time,the last two digits of the descriptor are shifted into the A OP buffer.

In FIG. 5C-17 the intput control signals are received by dual AND gate,S07_(b), and then fed to AND gate S06_(f'), whose output is connected toJK-D flip-flop M11_(q). The output of M11_(q) is fed to JK-D flip-flopM11_(r) and buffer driver M20_(a'). The output of flip-flop M11_(r) isfed to AND gate S06_(g), whose output connects to dual OR gate S09_(c)which feeds buffer S05_(j). The other output line of AND S06_(g') is fedto AND-OR gate S02_(d) having output lines to latches P14_(f) andP14_(g). These provide outputs of B buffer data and A buffer data.

FIG. 5C-18 is a flow diagram showing the sequential steps taken by theConnection Module 10_(tb). Discussion hereinafter will provide exemplaryexplanation in regard to how the Connection Module transmits the I/0descriptor andthe Descriptor Link from one of the OP buffers to theconnected Line Control Processor.

In FIG. 5C-19 the outputs of both OP buffers are connected to a seriesof multiplexors, M01_(y), M01_(z), M01_(a') through M01_(f'). The semultiplexors are the sources of the II0 bus. S1 and S2 are the inputselect terms for these multiplexors. The outputs of the multiplexors arefed to a series of buffer drivers, M20_(b') through M20_(m'). The driverenable terms (CEN and CEN/) control the selection of data placed on tothe II0 bus.

The "poll test" is the sequence that occurs by which the distributioncard 20_(od), in response to the connection request of the I0T 10_(t),attempts to make connection to a Line Control Processor. The sequentialsteps of the poll test operation are shown in FIG. 5C-20 and arediscussed subsequently in the text.

FIG. 5C-20a shows the decoding of the Line Control Processor address bythe Distribution Card. Tri-state buffers 83 and 84 provide the outputsignals of an address to a selected Line Control Processor. The buffersare fed by a pair of multiplexors 81 and 82. The multiplexors receivetheir input from decimal to binary decoders 75 and 80. Decoder 80 is fedby a four bit counter 76 which is clocked from NAND gates T3N_(a),T3NN_(b). Other control signals are developed from NAND gates T2N_(a),T2N_(b) and T4N_(a).

FIG. 5C-20b shows the basic circuit for the line direction control inthe Distribution Cards. This circuit uses a Hex buffer,BTSN_(a),_(b),_(c) and also NAND gates T2N_(c), T2N_(d) plus a Hexinverter TIN_(a). Discussion of the use of these circuits will bedescribed subsequently hereinafter.

FIG. 5C-21 is a flow chart of the Data Transfer Module 10_(tc). FIG.5C-21a shows more detail of the sequences in the Write cycle and FIG.5C-21b shows more detailed sequences in the Read cycle.

In FIG. 5C-22 the Write cycle data transfers between the informationregister (INR) N11_(k1), the output buffer 10_(0TB) and the characterregister M11_(m) are shown for modules 4 and modulus 2 addresses,indicating how portions of one register are transferred to portions ofanother register as will be described hereinafter. These registers wereshown in more detail previously in FIG. 5C-13.

FIG. 5C-23 shows various aspects of the Read cycle data transfers asamong the data transfer bus (DTB), the character register M11_(m) andthe output buffer 10_(OTB) for various directions of data transfer andfor various modulus numbers. A transfer control signal, XFER, enablesthe transfer of data from the DT bus to the OTB register; as seen inFIG. 5C-23, several types of transfer may occur depending on the OP-code(forward or backward) the modulus of the address, and the type oftransmission (word or character).

In FIG. 5C-24, there is shown a flow diagram indicating how the LCPresult descriptor (R/D) is stored as part of the data transfer sequence,number 09, DT09. Normally, at the data transfer sequence number 09, thestatus count of the LCP is STC--7 (true) and the Result Descriptor is onthe data lines. The Result Descriptor is then stored in the outputbuffer register (OTB) 10_(OTB).

FIG. 5C-25 is a flow diagram showing the "poll request" sequence as itoperates between the various parts of the system. The poll requestdetermines which one of several possible requesting Line ControlProcessors is to be granted access to memory and then to connect thatparticular Line Control Processor to the Input/Output Translator. Thesequence of the poll request has been described earlier in the text.

FIG. 5C-25a shows the priority encoding circuitry in the Base Modulewhereby any requesting Line Control Processor is provided with a basepriority number and then with a global priority number via jumpers whichcan be strapped at the time of installation. The Line ControlProcessor's request lines are patched through the base priority jumpersinto a priority encoder ENPO_(a). The outputs of the priority encoderare fed through inverters TIN_(a),_(b),_(c),_(d), over to a decoder 85(binary coded decimal to decimal decoder). The outputs of the invertersare also fed to a six-bit D register DR 60. The outputs of decoder 85then go through jumpers or straps which provide the global prioritynumber and are then fed to priority encoders ENPO_(b),_(c),_(d). Theoutputs of these priority encoders then go theough to NAND gatesT2N_(e),_(f),_(g) from which they are fed to the six-bit D register DR60. The outputs of the D register are fed to a decoder 86 (BCD todecimal decoder) thence through the Line Control Processor addressjumpers to the individual Line Control Processors. The global prioritynumbers from the D register DR 60 are fed to a Hex inverter 87 toprovide output signals which go to the Input-Output Translator 10_(t).

The global priority signals from the distribution card of each of theBase Modules (of FIG. 5C-1) are seen in FIG. 5C-26 connected to an 8-bitcomparator MO9_(a) which has outputs going to dual OR gate SO9_(d) andto AND gate SO6_(k'). Also coming from the Base Module distributioncards are the interrupt request lines from the top (T) and the bottom(B) of the driver cards. These inputs are fed to AND gates SO6_(h') andSO6_(i') whose outputs go to AND gates SO6_(j') and SO6_(1'). The globalpriority signals are also connected to OR gates P12_(a), P12_(b) andAND-OR gates SO2_(e), SO2_(f), SO2_(g) to provide the output prioritysignals for the first stage of priority resolution in the Input-OutputTranslator.

FIG. 5C-27 shows the second stage of global priority resolution in theInput-Output Translator. Basically the outputs of the first and secondresolution stages are compared to determine which of the 8 possible BaseModules has the highest global priority at that given moment. In thissecond stage, the highest priority from Driver Card 1 is compared to thehighest priority from Driver Card 2; concurrently the highest priorityform Driver Card 3 is compared to the highest priority from Driver Card4; then a final comparison determines the Base Module and the LCP whichhas the highest global priority. In the second stage, the prioritysignals from the Denver Card are connected to 8-bit comparators MO9A_(b)and MO9B_(c). The outputs of these comparators are fed to dual OR gatesSO9A_(e) and SO9B_(f). AND-OR gates SO2A_(h) and SO2A_(i) receive, fromthe Driver Cards, the signal inputs which are placed in a finalcomparator MO9A_(d) whose output feeds to a quad OR gate SO9B_(g).Signals from Driver Card 1 and Driver Card 2 are connected to tripleinput AND gates SO7A_(c),_(d),_(e),_(f), to provide the global priorityresolution signals.

The activities of the Reconnection Module 10_(t) are seen in thereconnection sequence of FIG. 5C-28 which shows the Reconnection Moduleflow. This reconnection sequence is initiated when an interrupt requestis received from one or more of the Base Modules.

In FIG. 5C-29 a multiplexor MO1_(n), receives address select inputs andthe reconnect address select, RCADSL, which occurs one clock time afterthe Channel Select. This selects the -2 volt inputs to the multiplexerin order to generate Address Select for all base driver distributioncards in the system.

III. DESCRIPTION OF OPERATIONS AND FUNCTIONS OF INPUT/OUTPUT TRANSLATORDESCRIPTOR LINK

During the execution of an I/O descriptor, the IOT handles all memoryaddressing functions for the LCP's, including incrementing the addressesand storing or retrieving them from scratchpad memory. Because LCPs maydisconnect and subsequently reconnect several times during the executionof a descriptor, and because each disconnection or reconnection requiresthat the LCP's address be stored in, or retrieved from, scratchpadmemory, the IOT needs some means to identify the location at which theLCP's descriptor addresses are stored. The IOT also must know iftranslation is required, if a backwards operation is specified, and ifthe data transfer to memory is to be inhibited. The descriptor link(FIG. 5D and Table IV) is the means by which the IOT is informed ofthese items.

The descriptor link (FIG. 5D) is originally assembled in the OP buffer(FIG. 5C-3), and is subsequently transmitted to the LCP during theconnection sequence. The descriptor link is transmitted twice, andstored in the LCP as two identical words.

As shown in FIG. 5C-3, the descriptor link is also transferred from theOP buffers onto the descriptor link bus (DLB). At the completion of aconnection or reconnection sequence, the data transfer start signal(DTSTRT) generates DLR←DL, which then generates the LDDLR levels. Theselevels then enable the loading of the descriptor link from the bus intothe descriptor link register illustrated in FIG. 5C-4.

During the data transfer sequence, the Data Transfer Module 10_(tr)generates SP←DLR, thus sending the address of the LCP to the addressscratched 10_(ams), FIG. 5C-2. The SP←DLR signal gates the six leastsignificant bits (the three base address bits and the three LCP addressbits) of the descriptor link to the scratchpad; the scratchpad respondswith the beginning address of the connected LCP's descriptor. At the endof the data transfer sequence, the modified beginning address is placedback into the LCP's scratchpad location.

Following a successful poll request in the reconnection sequence, theLCP transmits the descriptor link back to the IOT. At RC O2, FIG. 5C-28,the LCP transmits the first descriptor link word. As shown in FIG. 5C-5DLR←DAT and LDDLRA are generated, thus enabling the transfer of theselected data bus into a temporary holding register. The LCP transmitsthe second descriptor link word (identical to the first word) at RC O3,but because DLR←DAT is not generated, the word is not stored.

At the end of the reconnection sequence, the descriptor link istransferred from the temporary holding register into the selected datatransfer module's descriptor link register. Once the descriptor link isin the descriptor link register, FIG. 5C-4, the Data Transfer Module canbegin the operation specified by the LCP.

ADDRESSING

In order to transfer data to and from the correct memory locations, theIOT must have the ability to accept, store, and modify data fieldaddresses. The following text, along with FIG. 5C-2, describes how theIOT accomplishes these tasks.

ADDRESS STORE: FIG. 5C-2:

During the execution of an Initiate I/O instruction, the Processor10_(p) assembles the beginning (A) and the ending (B) addresses of thedata field. The Processor then transfers the complete A address from theProcessor NI register to the IOT address bus. At IIO3, FIG. 5C-15, ofthe IOT initiation sequence, the IOT generates WRITE and SPSBY, and thengates the base and LCP address bits to the scratchpad 10_(ps). Now, withthe channel's scratchpad location addressed and the Write enable active,the A address can be written into the scratchpad, FIG. 5F.

At IIO4, FIG. 5C-15, the Processor places the end address onto the IOTaddress bus, and again the IOT generates WRITE and SPBSY, along with thebase and LCP address. This time, however, the IOT also generatesADDRESB, thus causing the address on the bus to be written into the Baddress area of the scratchpad, FIG. 5F.

The begin and end addresses of the data field have now been stored inthe channel's address memory scratchpad. When the data transferoperation begins, these scratchpad locations will be accessed by theData Transfer Module 10_(tc).

ADDRESS MODIFICATION:

At the start of the data transfer operations, the Data Transfer receivesthe descriptor link, which includes the Base and LCP number. At DTO2,FIG. 5C-13, ADDRESB is generated, which with the Base and LCP number,addresses the channel's B word of the scratchpad, FIG. 5C-2. The Baddress is then transferred from the scratchpad 10_(ps) to the IOTaddress bus, ADxn, and from the bus through a multiplexer 63 to the IOTaddress register, 60. In the same manner, the A address is read (ADDRESBis not generated) and placed into the address register (ADDR 60) whilethe B address is being transferred from the address register to thecomparison register (CMR), 61.

When the Data Transfer Module enters either the Read or Write sequence(DTO5 or DTO3), FIG. 5C-13, a memory access is requested (MARF). Whenpriority is granted (PRIRTYx), the IOT transfers the begin addressregister to the address bus. The Processor 10_(p) then transfers theaddress from the bus to the memory address register, 10_(pam).

At MARF, Memory Access Request, time, the term ADDR-CMR is generated.This term causes the end address in CMR 61 to be subtracted from thebegin address in ADDR 60. During the execution of the Initiateinstruction, the Processor varifies that the A address is less than theB address; therefore, if the A address is less than 10 digits less thanthe B address, the six most significant digits of the result of thesubtraction will be equal to 9 because of borrows from the next highestdigit position. When this condition occurs (see example A below) theterm ALLNINE is generated. In backwards operations, essentially the sameprocedure is used, except that because the B address is in ADDR and theA address is in CMR (see example B, below), the result of thesubtraction would be all zeroes (ALLZER/) for the upper six digits whenthe addresses were less than 10 digits apart. ##STR7##

When ALLNINE or ALLZER/ is active, the least significant digit of theresult is used to generate ADCMP=n terms, where "n" indicates thedifference (in digits) between the A and B addresses. In forwardoperations, ALLNINE causes the 9's complement of the least significantdigit of the result to be used as "n"; in backwards operations, ALLZER/causes the unmodified least significant digit of the result to be usedas "n". The DT Module uses the ADCMP=n terms to determine when the endof the data field has been reached (ADCMP=0) or how much more dataremains to be transferred.

At GPL (Global Priority Resolution, FIG. 5C-26) time in Read operations,or at MAGF (Memory Access Granted) time during Write operations, thedata field address is modified. In forward operations, the A address inincremented, and in backwards operations, the B address is decremented.Because of the efficiency of word transfers with memory as compared tocharacter transfers, mod 4 addressing is used whenever possible;therefore, in most cases, the address is incremented or decremented by 4(ADDR4). There are instances, however, such as a mod 2 A address, or afinal character going to a mod 4 location, that require the IOT to havethe ability to modify the address by 2 (ADDR2).

Once the amount of incrementation or decrementation is determined, theincrement term (ADDR4 or ADDR2) is applied to the least significantdigit position of the adder 62. If a backwards operation is in progress,the MINUS level is also applied to the adder, forcing it to the subtractmode. Following the address incrementation, the modified address istransferred from the adder 62, through a multiplexor 63, back to the IOTaddress register 60.

ADDRESS RESTORE:

During the course of a data transfer operation, a LCP may disconnectfrom the IOT and begin communication with the peripheral device. Whenthe LCP is reconnected, data must be read from, or written into,locations contiguous with those used during the prior data transfersequence.

In order to do so, at the DT 07 (FIG. 5C-13) following a LCP disconnect,the IOT stores the current data field address in the channels'sscratchpad memory 10_(ps). Because the end address was not changed(assuming a forward operation), only the begin address need be stored.At DT 02 of the data transfer sequence following the reconnection of theLCP, the address is read from the channels's scratchpad and transferredto the address register 60.

OUTPUT BUFFER (OTB) SWITCHING LOGIC:

As previously mentioned, the IOT consists of an initiation module, aconnection module, one or two Data Transfer Modules, and a reconnectionmodule. In the course of IOT operation, it becomes necessary toestablish data and control paths from one of these modules to another,or from one of the modules to a LCP.

As shown in FIG. 5C-1, there are several different ways (shown as dottedlines) in which the paths can be established. The selection andestablishment of the data path are controlled by the OTB switching logic10_(OTB), and are based upon the channel number designated in theInitiate instruction and the availability of modules within the IOT. Thesubsequent text explaines how the paths are established, and how controlis passed from one module to another.

During the initiation sequence, the number of the base containing thedesignated LCP was decoded from the BF portion of the Initiate command.The decoded base number was then stored in one of the two OP bufferregisters (FIG. 5C-17) as ABASFn or BBASEn (n=1,2, or 4). At the sametime, AFULF or BFULF was set to indicate the buffer in use.

At CNOO, FIG. 5C-18, of the connection sequence, the ABASEn or BBASEnterms are used as input selects for a pair of multiplexors (MO1_(f),MO1_(g), See FIG. 5C-6). The inputs to these multiplexors are the busylevels from the four base driver cards. In this text, channel 43 is usedas an example of the designated LCP, and that AFULF is assumed to betrue. Channel 43 generates ABASE4, which allows CRD3BY/ (driver card 3not busy) to generate AN. AN allows ABASE4 to generate EN4, which isdecoded to CNENCH30, Connection Module Enable Channel 30. Because thisis not an extended result descriptor operation, AEXRDF/ (Extended ResultDescriptor) is true, thus enabling bus select BSEL to be generated.

BSEL goes to the OTB-COM card, (see FIG. 5C-7) where it attempts toconnect the Connection Module to one of the two data buses. As shown inFIG. 5C-1, there are four possible users for each data bus: two DataTransfer Modules 10_(tc), a Reconnection Module 10_(td), and theConnection Module 10_(tb). Each of the users has a flag which is set toindicate connection to one of the data buses. These flags and theconnections they indicate are shown in Table Va.

                  TABLE Va                                                        ______________________________________                                        Flag      Connection Indicated                                                ______________________________________                                        DT1AF     DT mod 1 to data bus A - (D.sub.A, FIG. 5C-1)                       DT2AF     DT mod 2 to data bus A                                              DT1BF     DT mod 1 to data bus B - (D.sub.B, FIG. 5C-1)                       DT2BF     DT mod 2 to data bus B                                              RCAF      RC mod to data bus A                                                RCBF      RC mod to data bus B                                                CNAF      CN mod to data bus A                                                CNBF      CN mod to data bus B                                                ______________________________________                                    

Any one of the flags of Table Va, is set, causes the appropriate databus busy flag (CHNAF or CHNBF) to be set. If one of the data buses isnot busy (CHNAF/ or CHNBF/), BSEL enables the setting of CNAF or CNBF,FIG. 5C-7, thus connecting the CN module to one of the data buses. Ifneither data bus is busy, CNAFJ is enabled, thus causing CNAF to set.

CNAFJ is one of the input select terms for the driver card bus enablelogic (see FIG. 5C-8). CNAFJ allows CNENCH 30 (from the CON MOD card,FIG. 5C-6) to set the ENBCHA30 flip-flop (FIG. 5C-8) thus enabling theconnection of driver card 3 to data bus A. CNAFJ also generates channelselect (CHSEL3/), which goes to the designated base to initiate the polltest sequence shown in FIG. 5C-20.

CNAFA (and CNBFA) are used to generate the multiplexor input selectterms shown in FIG. 5C-9. Because, in this discussion, CNAFA is true,S1A, S2A, S1AA, and S2AA are generated. These terms provide the controlrequired to establish the data paths between the various modules andbuses.

CNAFA also generates XMITA (see FIG. 5C-10). As shown in FIG. 5C-11,with S1A and S2A true, XMITA gates the IIO bus (which contains thedescriptor and link) onto data bus A (DAxn). If CNBFA had been set (FIG.5C-10), XMITB would have been generated, and the IIO bus would have beengated onto data bus B (DBxn).

Because ENBCHA 30 (FIG. 5C-8) has been set, data bus A (FIG. 5C-1) isgated onto driver card 3, 10_(d3), and from the driver card out to theBase. The Connection Module now has a path to the Base distribution card20_(od), FIG. 2 and FIG. 4A, and the poll test sequence can begin.

At the end of the connection sequence, FIG. 5C-18, (CNO8), CNDTSL isgenerated. As shown in FIG. 5C-12, if Data Transfer Module 1 is not busy(DT1BSY/), CNDTSL * CNAF generates DT1AF and CNAFK. If Data TransferModule 1 is busy but Data Transfer Module 2 is not busy, CNDTSL * CNAFgenerates DT2AF, thus connecting the second Data Transfer Module to thepreviously established data path. If CNBF had been set, DT1BF or DT2BFwould have been set by CNDTSL * CNBF in an equivalent logic circuit.

In FIG. 5C-12, if either DT1AF or DT1BF is set, DT1STRT is generated; ifDT2AF or DT2BF is set, DT2STRT is generated. The DTnSTRT terms are usedto start the data transfer sequence in the specified Data TransferModule.

The preceding text explained how a data path is established between adesignated LCP and the central system memory 10_(m). In the followingtext, the actions of the elements in the data path are described for atypical "word write" operation.

As shown in FIG. 5C-1, data enters the specified Data Transfer Modulefrom Main Memory 10_(m) via the Read bus (MRB), passes through the OTBdata path switching logic, and from there goes through the enableddriver card to the base containing the designated LCP.

A more detailed drawing of the Data Transfer Module, FIG. 5C-13, showsthat data from MRB(B_(10R)) goes to the IN register input multiplexorMO1_(min). Other inputs to this multiplexor are the CNDT bus (connectionerror flags), the IOT address register ADR (extended result descriptorinformation from the IOT scratchpad), and the maintenance bus Mbus. In anormal Write operation, INR←MRB occurs at each T2F time (FIG. 5C-21a) ofDTO3. INR←MRB generates MINS1 and MINS2, which, when true, select MRB asthe input to the IN register M11_(k),l. When LDINR is true at INR←MRBtime, the data from the Read bus is latched into the IN register.

The output of the IN register M11_(k),l, goes to the first of two OTBregister input multiplexors (OMB MPX), MO1_(p),q. The purpose of the OMBmultiplexor is to select either Read or Write data, and also to enablethe shifting and selection of either the first or second character of adata word. A one-character register (REG), M11_(m) is also an input tothe OMB multiplexor. The use of REG is explained in the data transfermodule logic flow.

Assuming a word Write operation and a mod 4 address, OTB←INR occurs atLCPSTF time of DT 03 (FIG. 5C-21). OTB←INR generates MOABS2 and MOCDS2,thus selecting the IN register M11_(k),l as the input to the OMBmultiplexor M01_(p),q.

The output of the OMB multiplexor goes to the translator 69, 70, andalso to the second OTM multiplexor, M01_(rs). The second multiplexorselects the untranslated data directly from the OMB multiplexor,translated data from the translator, result descriptor information fromvarious error flags, or information from the maintenance bus. In anormal Write operation with no translation, all select terms for the OTBmultiplexor are false, thus causing the output of the OMB multiplexorM01_(p),q to be selected as inputs.

OTB←INR also generates the OTB register load enable signal (LDOTB), thusallowing the data from the IN register to be latched into the OTBregister M11_(m),o. SEND, also generated at DT 03, then gates thecontents of the OTB register onto the DT1 bus (DT1xn..0).

The DT1 bus, FIG. 5c-13, is one of the inputs to the multiplexorM01_(k),l for the OTB data path switching logic shown in FIG. 5C-11. Theother inputs are the DT2 bus from the second Data Transfer Module, andthe IIO bus. In FIG. 5C-9, note that the input select terms for themultiplexors S1A, S1B, S2A, and S2B) are controlled by the Data TransferModule/Data Bus connection flip-flops (DTnxF). As shown in FIG. 5C-12,these flip-flops are controlled by the availability of the data transfermodules and data buses. The output of the multiplexor is then gated,FIG. 5C-11, onto the selected data bus (DAxn..0 or DBxn..0) by one ofthe transmit select levels (XMITA or XMITB). The transmit select levelsare controlled by the logic shown in FIG. 5C-10.

The data buses DAxn, DBxn, go to the base driver cards as shown in FIG.5C-14. AENB, which controls the selection of the data buses, isgenerated by the driver card enable term, ENBCHxn. In this case, becausechannel 43 is the designated channel, the ENBCHA30 flip-flop is set (seeFIG. 5C-8), thus generating AENB and enabling data bus A into drivercard 3.

In FIG. 5C-14, the output of the multiplexor M01_(t) goes through theBCML to CTL level changer S10_(a) to the inverters (ITSN), 71 and 72.These inverters gate the output of the level changers to one of the twobases connected to the base driver card. At the driver card, the basesare designated as top and bottom DINxnT and DINxnB. The even-numberedbases are connected to the top half of the driver cards, and theodd-numbered bases are connected to the bottom half of the driver card.

If an odd-numbered base is selected, the base address 1 bit (ABASE1 orBBASE1) is true; the presence of the 1 bit causes the term BOTTOMA0 orBOTTOMB0 to be generated, which in turn generates ENBB/. Because, inthis example, an even-numbered base (4), FIG. 5C-1, was selected, ENBB/is false, thus generating ENBT/, FIG. 5C-14, which enables the inverter71, 72 to gate the data out to the base.

INITIATION MODULE FLOW:

The purpose of the Initiation Module is to determine if an Initiateinstruction is for LCP channel, and if so, to receive and assemble theI/O descriptor information. The following text and FIG. 5C-15 explainhow the Initiation Module accomplishes these tasks.

When the Processor sends the channel number of the device to beinitiated (BF of the Initiate instruction), the IOT compares therequested channel number to those channels present in the IOT I/OSubsystem. If the channel number corresponds to an existing LCP channel,a signal OURCH is generated. OURCH then generates GO, which enables theSCDF and ICDF timing. These timings are used to synchronize the IOT withthe Processor 10_(p) and Memory 10_(m).

During the time BF is being decoded, the descriptor OP code is receivedfrom the Read bus. The OP code is decoded, and, if it is a legitmatevalue, OPOK is generated. If the decoded OP code is a cancel (OP=71+72),and the IOT is not busy, the cancel is valid and the term VALID isgenerated. VALID is also generated for non-cancel operations, if theyare not for channel 8 and the IOT is not busy.

Because BFULF is false, indicating that the entire descriptor has notyet been received, OPOK and VALID generate FILL at ICDL time. FILL thengenerates II+1 to increment the state counter of the Initiation Module,and also enables OPST.

OPST goes to OPBUFF card 1, where it generates LOADBOP. LOADBOP enablesthe loading of the base number, LCP number, and decoded OP code into theB OP buffer, FIG. 5C-17.

The initiation flow continues through its sequence, transferring aportion of the descriptor information from the memory Read bus into theB buffer at each state count. As shown in FIG. 5C-16, the B8 bit fromthe Read bus (MRB), (typical of all Read bus data) is multiplexed intovarious positions within the B buffer, dependent upon the state countand the associated register enable signal.

The preceding method is used for all transfers of descriptor informationto the Initiation Module, except for the transfer of the descriptors Aand B addresses, which use the following method.

At state count IIO3 (FIG. 5C-15) in conjunction with IOCPTIME, theprocessor sends the entire A address to the IOT via the processor-IOTaddress bus. The IOT generates WRITE and also gates the channel'sscratchpad address to address memory. The contents of the address busare then written into the channel's begin word of address memory. (Referto "Addressing", earlier discussed).

At state count IIO4, the same procedure is used, except that the IOTalso generates ADDRB, thus causing the address to be written into theend (B) word of address memory.

When the entire descriptor has been transferred to the IOT, theProcessor sends STCT * IOCF/ to signal the end of the transfer.Depending on the type of descriptor, STCF * IOCF/ may occur at IIO3 (noA or B addresses), IIO5 (space OP space count), or IIO7 (C address),FIG. 5C-15.

Because AFULF is not set (FIG. 5C-17), SHIFT . . . is true throughoutthe loading of the B OP buffer S02_(d). Therefore, SHIFTBA. and SHIFT .. O are also true, causing the descriptor data to be loaded into the AOP buffer S06_(g), one clock after it was loaded into the B OP buffer,S02_(d).

The B OP buffer is shifted to the A OP buffer at each clock, but becauseonly two digits of the B OP buffer change at any time, it appears asthough the data is being shifted from the B OP buffer to the A OP bufferin a series of two-digit transfers. As shown in FIG. 5C-17, when STCFand IOCF/ are true (indicating the end of the descriptor), BFULF is set,and at the same time, the last two digits of the descriptor are shiftedinto the A OP buffer, S06_(g).

Because BFULF is set, the next clock sets AFULF and clears BFULF, whichthen enables CLRB to clear the B OP buffer. Since SHIFTA/ and AFULF areboth true, SHIFT . . . is false, thus inhibiting the transfer of the BOP buffer (now all zeroes) into the A OP buffer.

When the A OP buffer is emptied, SHIFTA/ goes false, causing SHIFT . .and SHIFTBA to go true, thus forcing AFULF to the D e-set mode. BecauseBFULF is cleared, AFULF is cleared at the next clock.

If the IOT receives a second descriptor before the A OP buffer isemptied, AFULF and SHIFTA/ will be true, and SHIFT . . . will be false,thus allowing the descriptor to be stored in the B OP buffer, butinhibiting the transfer into the A OP buffer. If the entire descriptoris received before the A OP buffer is emptied, BFULF is set, and nofurther action occurs until one of the OP buffers is emptied.

If the Processor attempts an initiate operation to a LCP before the Bbuffer has been cleared (BFULF true), the OP Buffers Filled Flat(BUFFULF) is set. The IOT then decodes the BF of the attempted Initiatecommand to generate a result descriptor address, and subsequently writesa Result Descriptor (R/D) with bit 7 (OP buffers filled) set.

CONNECTION MODULE FLOW:

The following portion of the text, along with FIG. 5C-18, explains howthe Connection Module transmits the I/O descriptor and the descriptorlink from one of the OP buffers out to the connected LCP.

In FIG. 5C-19, note that the outputs of both OP buffers of FIG. 5C-17are connected to a series of multiplexors M01 which are the sources ofthe IIO bus. The input select terms for these multiplexors (S1 and S2),FIG. 5C-19, and the driver enable terms (CEN and CEN/), control theselection of the data that is placed onto the IIO bus. The status of S1and CEN is controlled by the state count of the connection module flow;the status of S2 is determined by the buffer being used.

Normally, OP buffer A is used; therefore, S2 is false and the A bufferinputs to the multiplexors are selected.

If, however, the driver card for OP buffer A's LCP is busy, and OPbuffer B contains a descriptor, BF (B Buffer In Use Flag, not to beconfused with BF of the Initiate instruction) is set, thus causing S2 tobe true and enabling the B buffer inputs to the multiplexors.

The IIO bus is an input to multiplexors which select sources for databuses A and B (see FIG. 5C-11). The bus selection is determined by CNAFand CNBF, one of which was set at BSEL time (CNOO, FIG. 5C-18).

CNAF and CNBF generate CNAFA and CNBFA, respectively. As shown in FIGS.5C-9 and 5C-10, CNAFA generates XMITA, S1A, and S2A, and CNBFA generatesXMITB, S1B, S2B. Once selected, the data bus transmits the descriptorinformation to the driver cards. The selected data bus goes to all basedriver cards; however, only the card connected to the designated LCP'sbase is enabled (ENBCHAn or ENBCHBn; see FIG. 5C-8).

During the time the IOT is selecting a data bus, it is also attemptingto establish a data path to a specific LCP. The Connection Modulereceives the decoded base and LCP address, and then sends a signal(Channel Select) to the proper distribution card. The poll test is themethod by which the distribution card, in response to the connectionrequest of the IOT, attempts to connect to a LCP. The sequence of eventsin the poll test operation is shown in FIG. 5C-20.

Following the transmission of Channel Select, the IOT sends the addressof the desired LCP via data lines D4, D2, and D1, FIG. 5E, to thedistribution card in the selected base. At the same time, the IOT sendsAddress Select to all bases in the system. The distribution card thatreceives both Address Select and Channel Select begins a poll test andresponds to the IOT with a LCP strobe; the distribution cards thatreceived Address Select only, consider it to be a busy signal, and areinhibited from communication with the IOT. When the IOT receives the LCPstrobe, it drops Channel Select.

As shown in FIG. 5C-20a, when the distribution card receives addressselect and channel select, PTACT/ (Poll Test Active) is generated. If noother distribution card in the base is busy, and there are no requestsfor access to the system, PTACT/ causes PTAFB to be generated. PTACT/also generates DCACKF←1. PTAFB enables the LCP address on data lines D4,D2, and D1 into a LCP address register, CR 40.

The BCD output of the LCP address register is decoded by decoder 80 toenable one of eight lines. Each line represents one LCP in the Base.

Vertical parity is checked on the LCP address. If there is no parityerror (PAROK), PTAFB sets PTCF (Poll Test Connect Flip-Flop) and LCPADF(LCP Address Flip-flop).

PTCF forces a pair of 2-to-1 multiplexors 81, 82 to select the output ofthe BCD to decimal address decoder as inputs. The other input to themultiplexors is from the poll request circuits. LCPADF enables thetri-state buffers 83, 84 (BTSN), thus gating the LCP address line ontothe base backplate.

When a LCP detects that its address line is active, that LCP responds tothe distribution card with the signal LCPCON (LCP Connected). WhenLCPCON is received in the distribution card, the Connect flip-flop(CONF) is set. If the base is not in local mode (a maintenancefunction), and CONF is set, the term CF * BL/ is generated.

Depending on the state of the I/O send line (IOSND/) from the connectedLCP, CF * BL/ activates either RECDATA/ (receive data) or SNDDATA/ (senddata). As shown in FIG. 5C-20b, SNDDATA/ and RECDATA/ control thedirection of the data lines between the LC and the IOT.

When the distribution card detects the absence of Channel Select, itresponds to the IOT with the LCP status, accompanied by a strobe. TheLCP is now connected to the IOT, and remains connected until the IOTdrops Address Select; the distribution card takes no further part in theIOT-LCP communications.

The preceding text outlined the events leading to a successfulconnection attempt; it should be noted, however, that the connectionattempt could have failed due to one of the following causes:

a. There was not a LCP at the location addressed, or the LCP at theaddressed location was off-line.

b. The LCP was busy (that is, LCP status was not 0 or 2 or 3).

c. The port was busy (that is, a second distribution card in the basewas busy).

d. A parity error was detected in the address.

The detection of any one of these errors would cause the connectionattempt to be aborted, and a result descriptor (R/D) indicative of thefailure to be written.

There now exists, via the IIO bus, one of the data buses, and theenabled base driver card, a data path from the OP buffer to the LCP BaseModule.

Portions of the descriptor are placed onto the IIO bus at the statecounts shown in the connection module flow chart, FIG. 5C-18. The IOTsends a strobe pulse (STIOF) with each portion of the descriptortransmitted; the LCP responds to each transmission with a strobe pulse(LCPSTF), accompanied by the LCP status count.

When the entire descriptor has been transmitted (indicated by receptionof STC=11 from the LCP), the IOT sets the Gate LPW flip-flop (GLPWF),thus enabling the transmission of the I/O descriptor LPW. The LCPresponds to the transmission of the LPW with a strobe pulse and thecurrent LCP status count.

The LCP may branch to any one of several status counts subsequent to thereception of the I/O descriptor and LPW. In this discussion, assume thatthe LCP returns a status count of 6 (receive descriptor link).

When STC=6 is detected, the flow goes to CNO5, FIG. 5C-18, where thefirst descriptor link word is transmitted. When the LCP acknowledges thereception of the first descriptor link word, the IOT sends the seconddescriptor link word and branches to CNO6. The second descriptor linkword, a retransmission of the first word, is not used by the system.When the reception of the second descriptor link word is acknowledged,the IOT transmits the descriptor link LPW, and then branches to CNO7.

At CNO7, the LCP status is again examined; if STC=4+7+8, the flowbranches to CNO8 to initiate the data transfer sequence. If STC=1, theAddress Select Flip-flop (ADSELF) is cleared, thus disconnecting theLCP.

The connection sequence is now complete; the LCP has the I/O descriptorand is free to begin transferring data from its buffer to the datatransfer module, or, if disconnected, to begin communication with itsassociated peripheral device.

DATA TRANSFER MODULE FLOW:

The following portion of the text, along the FIG. 5C-21, explains howthe data transfer module transfers data between memory and the connectedLCP.

DTO0 - IDLE:

The Data Transfer Module is initiated at DTO0 by the signal DTSTART,which may be generated in either the connection or the reconnectionmodule. At the time DTSTART is generated, the connection or reconnectionmodule also gates the descriptor link onto the descriptor link bus. WhenDTSTART is detected at DTO0, the Data Transfer Module transfers thedescriptor link from the bus into the Descriptor Link Register (DLR) 66.If there were any error flags set during the connection sequence, theyare stored in the IN register M11_(k),1, FIG. 5C-13, at DTO0 (INR←CN).

Assuming this to be the first time the data transfer module isinitiated, and that the initiation is not for a cancel operation, DT←O2occurs and the Read Scratchpad Flip-flop (RIDSPF) is set.

During the connection sequence, the beginning and ending addresses ofthe data field were stored in the initiated LCP channel's addressscratchpad. RIDSPF enables the floating logic to read the initiatedchannel's addresses from scratchpad memory and place those addressesinto the appropriate registers. To do so, RIDSPF gates the scratchpadaddress (decoded from the LCP channel number) from DLR to the scratchpad(SPAD←DL), then gates the output of the addressed scratchpad into theaddress register (ADDR←ADB). The previous contents of the addressregister are shifted to the comparison register (CMR←ADDR), and RIDSPFis cleared.

DTO2 - ADDRESS FETCH:

On the initial pass through DTO2 during a forward operation, ADDRESB isenabled, concurrent with the floating logic enabled by RIDSPF at DTO0.ADDRESB is used as the most signficant bit of the scratchpad address,and as such, causes the end address to be read by the floating logic. Onthe second pass through DTO2, ADDRESB is inhibited; therefore, whenRIDSPF is set, the begin address is read from scratchpad and transferredto the address register 60, FIG. 5C-2, and the end address istransferred from the address register to the comparison register 61.When the addresses are read from scratchpad, their boundaries arechecked; if the end address is on a character boundary (MOD2), the EndAddress Mod 2 Flip-flop (EMOD2F) is set; if the beginning address is mod2, the Begin Address Mod 2 Flip-flop (MOD2F) is set.

At the end of the address fetch cycle, ADDR-CMR occurs, causing the endaddress in CMR 61 to be subtracted from the begin address in ADDR 60.Because the Processor has already verified that the end address islarger than the begin address, the result of the subtraction, expressedas ADCMP=n, where "n" is the absolute difference, indicates the amount(in digits) by which the begin address may be incremented beforebecoming equal to the end address.

After the second address has been read, the data transfer moduleexamines the LCP's status count; if STC=8 is true, the flow goes to DTO3to begin the Write cycle. If an Extended Result Descriptor operation isin progress, the flow remains at DTO2. IF STC=4 is true, the flow goesto DT O5 to begin the Read cycle.

DTO3 - WRITE CYCLE:

The Write cycle begins by setting MARF, thus requesting a memory cyclefor the data in the location specified by the contents of ADDR. MARFenables the address comparison (ADDR-CMR), and, when the Data TransferModule gets priority (PRIRTYX), transfers the memory address from theIOT address register 60 to the Processor's memory address 10_(pam)(ADB←ADDR). When memory control responds (GPL) to the access request,MARF is cleared, MAGF is set, and the results of the address comparisonare examined. If the begin address is not at least 4 less than the endaddress, IOCBF is set.

At MAGF time, the begin address is incremented. If MOD2F is set,indicating that the begin address is mod 2, the address is incrementedby 2(ADDR2), thus advancing the address to a mod 4 value. If MOD2F isnot set, the address is incremented by 4 (ADDR4) to the next word.

Subsequent to the incrementation, the address is restored to the addressregister (ADDR←ADD). Restoration of the address causes the floatinglogic to generate LDADDR as the direct-set level for the register, andMADRS2 as the MUX select level to gate the output of the adder into theaddress register.

MAGF also causes MAGF←0 and T2F←1. At T2F time, FIG. 5C-21a, therequested data is received from memory and stored in the IN register(INR←MRB), the IN register full flag is set (INF←1), and T2F is cleared.

Now, the INF set, XFER, which is used as an enable term to load variousdata registers, is generated.

If the begin address is mod 4, XFER enables the transfer of the dataword from the IN register to the OTB register (see FIG. 5C-22), sets theOTB register full flag (OTBF←1), and sends a strobe (STIOF←1) to theLCP, signaling that data is available.

If the begin address is mod 2, memory control reads only one byte, andthen places that byte on both halves of the Read bus. At T2F time, thetwo duplicate bytes are transferred from MRB into INR. At XFER time, themost significant byte in INR is transferred to the least significantbyte of OTB (OTCD←INAB), the least significant byte is transferred tothe character register (REG←INCD), and contents of the characterregister M11_(m) are transferred to the most significant byte of OTB(OTAB←REG), and INF is cleared.

If GOFF is set, indicating a mod 2 address, OTBF←1 and STIOF←1 areinhibited, and the character in OTB is not transmitted to the LCP.Detection of INF/ and OTBF/ causes a request for a new memory cycle. Atthe previous MAGF time, the address was incremented by 2; the address isnow mod 4, so the memory cycle results in an entire word being read frommemory and placed into INR.

Once set, MOD2F remains set throughout the operation, even though thebegin address is no longer mod 2; therefore, at XFER time, the transfersfrom INR to REG and OTB occur as before. As shown in FIG. 5C-22, thefirst character read, which is now in REG, is transferred to OTAB, andthe most significant character in INR is transferred to OTCD. GOFF iscleared at XFER time, so the OTB full flag can be set, and a strobepulse can be sent to the LCP to signal that data is available. The leastsignificant character in INR is transferred to REG, where it will remainuntil the next cycle causes it to be transferred to OTAB.

A new memory cycle is requested when INF is cleared, indicating that INRhas transferred its data to OTB (or to OTB and REG, if MOD2F is set), orwhen OTB is empty (OTBF/), and a LCP strobe is detected, indicating thatthe data in INR is going to be transferred before the new data canarrive from memory. Memory cycles continue until the end of the memorydata field is reached (indicated by IOCBF←1), or until the LCP signals achange of status, indicating that no additional data is required (thatis, an ending code was detected, or the LCP data buffer is full).

If IOCBF is detected, the IOT sets TERMF, thus causing the TERMINATElevel to be sent to the LCP along with the last data transfer. Upondetection of TERMINATE, the LCP changes its status from 8 to 14. At STC14, the LCP must be informed if the last data transferred consisted of aword or a character. In order to do so, the IOT examines the begin andend addresses of the data field to determine if the total number ofcharacters transmitted was odd or even; if the term (MOD2F (+) EMOD2F)is false, indicating that both the begin and end addresses were mod 2,or that they were both mod 4, an even number of characters was sent, andthe last transmission consisted of a full word. Because the lasttransmission consisted of a full word, TERMF is cleared and theTERMINATE level is dropped; the absence of TERMINATE indicates to a LCPin STC 14 that the last transmission consisted of a full word.

If the term (MOD2F (+) EMOD2F) is true, indicating that the beginaddress or the end address, but not both, is mod 2, there were an oddnumber of characters sent, and the last transmission consisted of onlyone character. In this case, TERMF is not cleared, nor is TERMINATEdropped. The detection of TERMINATE indicates to a LCP in STC 14 thatthe last transmission consisted of one character only.

If, due to some error, the LCP does not go to STC 14 following thedetection of TERMINATE at STC 8, and the last transmission consisted ofonly one character, the LCP data buffer address will have beenincremented one character position too far; in this case, the IOT setsthe Address Error Flip-flop (ADDERF←1), and reports the condition in theIOT result descriptor.

Once the LCP has determined whether a word or a character wastransferred, the status is changed from 14 to 12.

As previously mentioned, the LCP can halt the data transfer operation bychanging status, typically going from STC=8 to STC =12. If the LCPinitiates the halt, there is a possibility that the IOT has already readthe next word and incremented the address. In this case, the LCP cannotaccept the word; therefore, the IOT must decrement the address so as toenable the rereading of the word at some future time.

When STC=12 is detected, and there is no data being held in the IOT(OTBF/ and INF/), the flow exits to DT04 (Write Break).

DT04 - WRITE BREAK:

Upon entry into DT04, a LCP is typically at STC=12; when the IOT detectsSTC=12, a strobe pulse is sent to the LCP, and GOF, which enables thetransmission of the longitudinal parity word, is set. The LCP respondsto the strobe pulse by changing its status to one of the following:

a. STC=1 Disconnect

b. STC=7 Result descriptor (i.e., end of operation)

c. STC=9 Encoded status (i.e., address modification may be required).

d. STC=13 Break enable (i.e., the LCP requests to return to the Writecycle).

DT05 - READ CYCLE:

The Read cycle begins by setting MARF, and transferring the data fieldaddress from ADDR to the Processor's memory address register (FIG.5C-2). Concurrent with the setting of MARF, the IOT generats XFER andsends a strobe pulse to the LCP.

XFER enables the transfer of data from the DT bus to the OTB register.As shown in FIG. 5C-23, there are several types of transfers that mayoccur, depending on the OP code (forward or backward), the mod of theaddress, and the type of transmission (word or character). At GPL time,the address is incremented, and at MAGF time, the data in the OTBregister is written into memory.

The IOT waits for a LCP strobe pulse; when the strobe is detected, MARFis set and the next memory cycle begins. Memory cycle continue until thedata field is filled, in which case the IOT sets the Terminateflip-flop, thus indicating to the LCP that no more data can be accepted,or until the LCP signals that there is no more data to be transferred.

Detection of a strobe pulse from the IOT accompanied by the TERMINATElevel causes the LCP to change status from STC=4 (Read) to STC=12(Break). When the IOT detects STC=12, it sends another strobe pulse tothe LCP. This strobe causes the LCP to change status to either STC=1(Disconnect), STC=7 (Result descriptor), STC=9 (Encoded status), orSTC=13 (Break enable). When one of these status counts is detected, theIOT goes to DT 06.

DT06 - READ BREAK:

The Read Break state is used to check for longitudinal parity errors inthe data received in DT05, and also to examine the LCP status so as todetermine the next action the IOT must take.

Detection of a LCP strobe pulse at DTO6 causes GOF and TERMF to becleared. The LCP status which accompanied the strobe pulse is examined;if the status indicates disconnect (STC=1) or result descriptor (STC=7),the flow is forced to DT07 to store the current data field address. IfSTC=9 (encoded status) accompanied the strobe pulse, the IOT respondswith an IOT strobe (STIOF←1) and goes to DT11 to examine the encodedstatus.

A status count of 13 indicates that the LCP is requesting a return tothe Read cycle (DT05). The IOT acknowledges the LCP request by settingGOF and returning a strobe pulse to the LCP. If, due to some otherrequest (BSEL or EMREQ), the LCP cannot be returned to the Read cycle,TERMF is set, causing the TERMINATE level to be sent to the LCP.Detection of TERMINATE in the LCP causes the status to change fromSTC=13 to STC=1; when the IOT detects STC=1, it goes to DT07 (storeaddress).

If the request by the LCP for a return to the Read cycle is granted, astrobe pulse is sent by the IOT, but TERMF is not set. Detection of anIOT strobe and TERMINATE/ causes a LCP at STC=13 to change status toSTC=4. When the IOT detects STC=4, the flow returns to the Read cycle(DT05).

The last transmission during the Read cycle (when the LCP was atSTC=12), consisted of the LCP LPW. If there had been no errors duringthe Read cycle data transmissions, the reception of the LCP LPW wouldhave cleared the IOT LPW.

Upon reception of the first LCP strobe in DTO6, the IOT LPW is examined;if it is not cleared, the Longitudinal Parity Error Flip-flop (LPERRF)is set.

If any of the error flip-flops have been set, GOF is set and the statusof the error flip-flops transferred to the address register (ADDR←RD).RITSPF, which was cleared by the scratchpad write floating logic, isagain set, causing WRITE to be generated. WRITE and GOF cause EXRDW1 tobe generated, which causes the contents of the address register to bewritten into the first extended result descriptor word. Concurrent withthe generation of EXRD1, GOF causes DT←00 to occur, forcing the flow tothe idle state.

If the LCP has completed its operation and is going to write a resultdescriptor (STC=7), the data field address is restored to the channel'sscratchpad, and a strobe pulse is sent to the LCP. When WRITE isdetected, the flow goes to DT09 to store the result descriptor, andLCPRDA is generated.

LCPRDA is used to determine the memory address of the LCP channel'sresult descriptor, and then to place that address into the addressregister. The result descriptor address is specified by the expression(CH×20) +108, where CH is the channel number of the LCP.

DT09 - STORE LCP RESULT DESCRIPTOR:

In response to the I/O strobe received from the previous state, the LCPreturns its status, accompanied by a LCP strobe. As shown in FIG. 5C-24,upon reception of the LCP strobe at DT09, the status is examined; atthis time, status should indicate that the LCP is in one of thefollowing states:

a. STC=2 (Not Ready)

b. STC=3 (Ready)

c. STC=7 (Result Descriptor)

d. STC=15 (Result Descriptor LPW)

Any other status is illegal and will be flagged as such.

STORE RESULT DESCRIPTOR:

In the course of a normal operation, STC=7 is true when the flow entersDTO9, and the result descriptor is on the data lines. The resultdescriptor is stored in the OTB register, GOF is set, and a strobe pulse(ST1OF←1) is sent to the LCP. A memory cycle is requested for thechannel's result descriptor location (specified by LCPRDA in theprevious state), and the result descriptor in OTB is written into mainmemory.

When the next (second) LCP strobe is received, the LCP status is againexamined; this time, the status should indicate that the resultdescriptor LPW is on the data lines (STC=15), or that an extended resultdescriptor is to be written (STC=7).

Assuming STC to be 15, the LPW from the LCP is stored in OTB; at thesame time, the LPW being assembled in the IOT is incremented by the LCPLPW. If there have been no errors in the transmission of the resultdescriptor, the addition of the LCP LPW will clear the IOT LPW; if theIOT LPW is not cleared, the Longitudinal Parity Error Flip-flop (LPERF)is set to flag the error. Because GOF is set, there is no request formemory access; the flow idles until the next LCP strobe is detected.

Typically, the status count accompanying the next LCP strobe indicatesthat the LCP is Not Ready (STC=2) or Ready (STC=3); in either case, GOFis cleared and Address Select is dropped (DT×ASL←0), thus disconnectingthe LCP. The flow then goes to DT10.

STORE EXTENDED RESULT DESCRIPTOR:

If, upon detection of the second LCP strobe, the status count is 7, theresult descriptor information from the LCP is stored in OTB as was donefollowing the first LCP strobe. Because GOF is set, there is no memoryaccess request; instead, the Extended Result Descriptor Flip-flop(EXRDF) is set. EXRDF enables the transfer of the contents of OTB to theIOT address register, and initiates the floating logic whichsubsequently transfers the contents of the address register to thechannel's scratchpad memory. EXRDF also generates EXRD1, which is usedwith the scratchpad address to specify the location in scratchpad memoryfollowing that of the channel's end word.

Detection of a third LCP strobe accompanied by STC=7 causes essentiallythe same events to occur; i.e., the result descriptor information isreceived from the LCP and stored in the OTB register, transferred fromOTB to the address register, then transferred from the address registerto scratchpad memory. During this sequence, GOFF, which was set with thefirst extended result descriptor word was stored, enables ADDRESB, whichwith EXRD1 causes the data from the address register to be written intothe scratchpad location following that of the first extended resultdescriptor word.

After transmitting the second extended result descriptor word, the LCPsends a strobe, this time accompanied by STC=15 and the resultdescriptor LPW. From this point, the flow is the same as the basicresult descriptor store flow; i.e., at STC=15, the LPW is checked, atSTC=02 or 3, the LCP is disconnected, and the flow goes to DT10.

DT10 - STORE IOT RESULT DESCRIPTOR:

The IOT result descriptor stored at DT10, FIG. 5C-21, may be the resultof a LCP descriptor completing, in which case the result descriptor isstored in the main memory location specified by the equation(CH×20)+100, where CH is the channel number of the initiated LCP, or itmay be the result of an IOT cancel descriptor (OP 71 or OP 72)completing, in which case the result descriptor is stored in main memorylocation 260 (channel 8 result descriptor area).

Assuming that this pass through DT10 is the result of a LCP operation,GOF is in the cleared state, thus allowing the error flags (LPERF,VPERF, ILSTCF, etc). to be transferred to the OTB register (OTB←RD). GOFis then set, and a memory cycle is requested for the LCP channel'sresult descriptor location. At MAGF time, the result descriptor word inOTB is transferred to the Write bus, and a signal (INTJ) is sent to theProcessor to indicate that a result descriptor has been written.Subsequently, the Channel Busy Flip-flop is cleared, and the flow goesto the IOT idle state, DT00.

If DT10 is entered as a result of an IOT cancel operation (OP 71 or OP72), GOF is in the set state, indicating that the result descriptorinformation is already in the OTB register as a result of the actions inDT00; therefore, OTB←RD is inhibited. A memory cycle is requested, thistime for the channel 8 result descriptor location (260), and the IOTresult descriptor is written. The IOT Busy Flip-flop is cleared and theflow goes to the IOT idle state, DT00.

DT11- ENCODED STATUS:

During a read or write operation, the IOT increments the A address by 4for each data transfer. Therefore, if the first character of a wordtransferred between the IOT and the LCP happens to be an ending code,the LCP's A address will have been incremented two digits beyond the endof the message.

The LCP signals the IOT that the first character was an ending code byraising STC=9 during the IOT Read or Write sequence (DT05 or DT03). Upondetection of STC=9, the IOT flow leaves the Read or Write sequence, goesto the appropriate break state, and from the break state, goes to DT11.During this time, the LCP has changed its status to either 1 or 7, andset the D1 bit on the data bus to indicate that the address must bemodified.

At DT11, when STC=1+7 is detected, the flow is forced to DT07 to restorethe A address to the channel's scratchpad memory. If the D1 data bitfrom the LCP is on at DT11, the begin address is decremented by 2 priorto writing it back into the address scratchpad.

RECONNECTION MODULE FLOW

After having been connected to the IOT and receiving the descriptor anddescriptor link, a LCP may disconnect from the system in order tocommunicate with its associated peripheral device. If that LCPsubsequently requires access to memory, it must re-establish aconnection and return the descriptor link to the IOT.

When a LCP requests access to memory, it sends a signal (LCPRQ) to thebase distribution card 20_(od). In response to the request by the LCP,the distribution card initiates a "poll request" operation.

POLL REQUEST:

The poll request determines which one of several possible requestingLCPs is to be granted access, and then connects that LCP to the IOT. Asshown in FIG. 5C-25, the poll request is initiated when a LCP activatesits request line (LCPRQ). The distribution card then resolves any basepriority conflicts that may occur, and forwards an interrupt requestsignal (IP) to the IOT. If the IOT has a Data Transfer Module available,it responds to the distribution card with the Access Granted (AG)signal. Upon receipt of AG, distribution cards in bases havingrequesting LCPs send the global priorities of those LCPs to the IOT.

The IOT determines which distribution card sent the highest globalpriority, and then responds to that distribution card with AddressSelect and Channel Select. The other distribution cards with lowerglobal priorities receive Address Select only, which indicates to themthat their requests were denied, and that they must initiate anotherpoll request.

The distribution card that receives both Address Select and ChannelSelect activates the address line of the requesting LCP. When the LCPdetects its address, it enables its backplane receivers and drivers, andthen responds to the distribution card with the LCP connected signal,LCPCON.

Upon receipt of LCPCON, the distribution card sends a strobe pulse(LCPST) to the IOT as an indication that the LCP is connected. Detectionof LCPST causes the IOT to drop Channel Select and Access Granted, thusending the poll request portion of the reconnection sequence.

PRIORITY:

For those instances when two or more LCPs simultaneously request areconnection, a 2-level priority resolution scheme has been implemented.This scheme considers priorities both internal and external to the LCPBase Module.

BASE PRIORITY:

The internal priority resolution scheme (Base Priority) determines whichone of the several possible requesting LCPs within a base is to beallowed to compete with LCPs from other bases for access to the IOT. Thebase priority for each LCP is set by strapping on the distribution card.The base priority for a LCP may be any value from 0 (lowest) to 7(highest); no two LCPs within the base may have the same base priority.The selection of the base priority value is dependent upon the relativetransfer rates of the peripheral devices. Those LCPs connected to hightransfer rate devices, such as magnetic tape or disk pack, are typicallyassigned the higher piorities (4 through 7), and those LCPs connected tolow transfer rate devices, such as card readers, printers and operatorterminals, are assigned the lower priorities.

If a base contains only low transfer rate LCPs, those LCPs may beassigned the higher priorities (4 through 7); conversely, if the basecontains only high transfer rate LCPs, they may be assigned the lowerpriorities (0 through 3). If a base contains two or more of the sametype of LCP, those LCPs may be assigned sequential priority values. Asshown in FIG. 5C-25a, the request lines (LCPRQn/) from the LCPs arestrapped to the inputs of a priority encoder (ENPO).

The output of the encoder is the BCD equivalent of the highest valueinput; that is, the requesting LCP with the highest base priority.

GLOBAL PRIORITY:

Once base priority has been resolved, a LCP must contend with LCPs fromother bases for access to the IOT. Global priority resolution is themeans by which a LCP is selected from the several possible requestingLCPs. Global priority is assigned (by strapping) at installation time,and is based upon the absolute transfer rate of the LCPs associatedperipheral device. The global priority may be any value from 1 (for alow-speed device) to 6 (for a high-speed device). It is acceptable tohave more than one LCP with the same global priority in a base.

As shown in FIG. 5C-25a, the BCD output of the base priority resolutionencoder is the input to a BCD-to-decimal encoder (DCBO). Each of theGPADn/ output lines from the DCBO is jumpered to the appropriate pin orpins of a group of three ENPOs, to generate the desired global priorityvalue (see detail A in FIG. 5C-25a). Note that if a LCP activates itsemergency request line (EMREQ), a global priority of 7 is generated.

The distribution card holds the global priority value until the IOTsends Access Granted. When Access Granted is detected, the distributioncard sends the global priority to the IOT on data lines D1 through D4.

If an IOT data path is available when an interrupt request is received,the IOT sends Access Granted (AG) to all distribution cards in thesystem. When the individual distribution cards detect AG, send theglobal priority levels of their requesting LCPs to the IOT. The IOT thenexamines the global prioritites to determine which is the highest.

The IOT may have up to four base driver cards, with each card dividedinto two sections (top and bottom). Each half of each driver card canconnect to one of the eight bases that may be in the system.

In the IOT, the global priority values from the distribution cards arebused to the global priority resolution circuits. The global prioritylevels from the two distribution cards that may be connected to eachbase driver card are compared, FIG. 5C-26. A signal is generated whichindicates that either the top or bottom half of the driver card receivedthe highest priority value. The half receiving the highest priority fromits associated distribution card then forwards that priority to the nextstage of comparison, FIG. 5C-27.

In the next stage, the highest priority from driver card 1 is comparedto the highest priority from driver card 2, and the highest priorityfrom driver card 3 is compared to the highest priority from driver card4. As shown in FIG. 5C-27, the outputs of these two stages are compared,thus determining which of the eight possible bases has the highestglobal priority.

IOT RECONNECTION SEQUENCE:

The RC sequence (shown in FIG. 5C-28) is initiated when an interruptrequest is received from one or more of the bases. Detection of theinterrupt generates INTREQ, which, at RCOO, generates RCNECT.

RCNECT goes to the RCN-COM card, where it sets the Reconnect Flip-flop(RCNCTF), which enables the selection of an IOT data bus (RCAF or RCBF;see previous discussion on "OTB Switching Logic" and FIG. 5C-7). Theselection of RCAF or RCBF also generates RCSTART on the OTB-COM card.

RCSTART increments the RC counter (RC+1), and also sets the AccessGranted Flip-flop, thus causing AG to be sent to all bases. In responseto Access Granted, the requesting distribution cards send theirindividual global priorities to the IOT. The IOT compares the globalpriorities of the requesting distribution cards, and then sends theChannel Select signal to the requesting distribution card having thehighest global priority.

As shown in FIG. 5C-29, RCADSL, which occurs one clock after ChannelSelect, selects the -2 volt inputs to the multiplexor, thus generatingAddress Select for all base driver and distribution cards in the system.

The distribution card that receives both Channel Select and AddressSelect responds to the IOT with a LCP strobe, then sets its LCP AddressFlip-flop, thus driving the address line of the requesting LCP. When theLCP detects that its address line is active, it responds to thedistribution card with the LCP connected signal (LCPCON).

Upon receipt of the LCP strobe, the IOT drops Access Granted and ChannelSelect; when the distribution card detects the absence of Access Grantedand Channel Select, and the presence of LCPCON, it assumes theconnection to be completed, and responds to the IOT with LCP strobe,accompanied by the LCP status.

The poll request is now complete; the distribution card takes no furtherpart in the LCP-IOT communication. The LCP and the IOT continue with thereconnection sequence until the LCP is connected, after which control ispassed to the IOT Data Transfer Module. The LCP remains connected untilthe IOT drops Address Select.

Following a successful poll request (RC 02), FIG. 5C-28, the IOTreceives and stores the descriptor link. At RC 03, the LCP transmits thesecond descriptor link word, but because DLR←DAT is not generated, noinformation is stored. The second descriptor link word does, however,increment the LPW.

At RC 04, the descriptor link LPW is received, and at RC 05, the LPW ischecked. If the LPW is correct, the flow goes to RC 06 , where RCDTSL isgenerated.

RCDTSL enables the selection of a Data Transfer Module, and alsogenerates the appropriate start signal for that module. The DataTransfer Module then assumes control and begins communications with thereconnected LCP.

Message Level Interface:

As was previously described in reference to FIG. 2, the LCP Base Module20₀ is typical of the other Base Modules in that each individual BaseModule contains a Distribution Card 20_(0d) which services up to eightLCP's. In addition, each LCP Base Module has a Maintenance Card such as20_(0m) and a Termination Card 20_(0t).

The Distribution Card for each LCP Base Module provides an interfacebetween the LCP Base Module and the Input-Output Translator 10_(t) ofthe Main System 10. As seen in FIG. 2, the message level interface 15provides a channel to the IOT 10_(t) from each LCP Base Module by meansof 25 lines. These lines are shown in FIG. 5E. The functions of each ofthese individually identified lines are listed in Table VI herein below:

                  TABLE VI                                                        ______________________________________                                        (Refer to FIG. 5E also                                                        Signal Name                                                                            Description                                                          ______________________________________                                        ADDSEL   Address Select. This signal, when active,                                     indicates that the IOT is connected to, or                                    is attempting to connect to, a specific LCP.                                  Once the connection is made, the LCP remains                                  connected until the IOT drops ADDSEL.                                AG + SIO Access Granted or Strobe I/O. If an LCP                                       is not connected; this signal indicates that                                  the LCPs request for reconnection has been                                    granted, and initiates the "Poll Request"                                     algorithm. If the LCP is connected, this                                      signal is the IOT's acknowledgement for                                       information received, or strobe for information                               transmitted.                                                         TRM + MC Terminates or Master Clear. If no LCP's are                                   connected, this signaL will cause all on-line                                 LCP's to clear. If an LCP is connected, this                                  signal will terminate the connected LCP.                             LCPST    LCP Strobe. If aN LCP is connected, this                                      signal is the LCP's acknowledgement for                                       information received, or the strobe for                                       information transmitted. This signal is                                       also used by the Distribution Card as an                                      acknowledgement during Poll Test and Poll                                     Request.                                                             ER + ST8 Emergency Request or LCP Status 8.                                            When activated by an unconnected LCP, this                                    signal indicates that the LCP requires                                        immediate access to the IOT. If activated                                     by a connected LCP, this signal indicates                                     that bit 8 of the LCP status is set.                                 IP + ST4 Interrupt Request, Poll Test Parity Error,                                    or LCP Status 4. When activated by an                                         unconnected LCP, this signal indicates that                                   the LCP requires access to memory, i.e., the                                  LCP is requesting a reconnection. If                                          activated during a system-initated connection                                 sequence (Poll Test), this signal indicates                                   that a parity error was detected during the                                   Poll Test. If activated by a connected LCP,                                   IP + ST4 indicates that bit 4 of the LCP                                      status is set.                                                       PB + ST2 Port Busy or LCP Status 2. When detected                                      during a Poll Test, this signal indicates                                     that the LCP Base is "busy". If activated                                     by a connected LCP, PB + ST2 indicates that                                   bit 2 of the LCP status is set.                                      CS +  ST1                                                                              Channel Select or LCP Status 1. When                                          activated by the IOT and transmitted to an                                    LCP Base, this signal indicates "channel                                      select", and that a connection or                                             reconnection attempt has been initiated. If                                   activated by a connected LCP, CS + ST1 indicates                              that bit 1 of the LCP status is set.                                 PARITY   Parity. This bidirectional line carries                                       the proper (odd) parity for the information                                   on the 16 data lines.                                                DATAxn   Data Lines (x = A, B, C, or D; n = 1, 2, 4, or                                8). In the unconnected state, these 16                                        bidirectional lines are used for addressing                                   and priority resolution in connection or                                      reconnection attempts. In the connected                                       state, these lines are used for the                                           transfer of data between the IOT and the LCP.                        ______________________________________                                    

The message level interface 15 (MLI) which consists of 25 signal linesconnecting the Distribution Card as 20_(0d), of a particular LCP BaseModule as 20₀, to the IOT 10_(t) provides assurance that the signaldiscipline presented to the IOT is a standard one regardless of thevariations of logic and operation found in the different types of LCP's.It will be noted that some of the MLI signal lines 15 shown in FIG. 5Eare bidirectional, and are assigned multiple functions, depending on thesource of the signal and the state (connected or disconnected) of theLCP.

The Distribution Card 20_(0d) for a given LCP Base Module is used toprovide a part of the Message Level Interface between the IOT and theindividual LCP's within the Base Module. The Distribution Card alsoworks in conjunction with the IOT Connection Module 10_(tb) to establisha data path to a specified LCP (Poll Test), and, upon request by an LCP,works with the IOT Reconnection Module 10_(td) to establish a path fromthat particular LCP to the IOT (Poll Request).

LCP Status Counts:

During the time a particular LCP is connected, it follows a standardcommunication procedure with the IOT. Although the sequence of eventsfollowed in the communication procedure may not be identical for allLCP's, the events occurring in any one point in the sequence will beidentical.

The steps in the sequence, which are numbered 0 through 15, are called"Status Counts" and are transmitted to the IOT. The IOT examines the"Status Counts" each time it receives a strobe pulse from the LCP and,based upon that status count, takes appropriate action. More detail inthe sequence and use of status counts will be provided hereinafter. FIG.6A is a diagram showing the various status counts and the logic flowwhich they involve. Detailed explanation of this logic and the statuscounts involved will be provided hereinafter.

LCP Base Module Backplane:

A local common backplane is provided in each of the LCP Base Modules20₀, 20₁, 20₂, etc. Each backplane connects to all the eight LCP's inthe Base Module. The backplane is constructed so that all signal linesare bussed the length of the backplane, thus making each line availableto all LCPs in that Base Module. From the individual position of asingle LCP, these backplane lines fall into two general types: (a) thosegoing to the Distribution Card and on to the IOT; and (b) those going tothe Maintenance and Termination Cards. With the exception of the variousclock and voltage lines, those lines going to the Maintenance Card,(such as for example, 20_(0m) of FIG. 2) are used for local or off-linemaintenance functions.

Of those lines which go to the Distribution Card, and on to the IOT,some, such as the data and the parity lines, must be gated to individualLCPs. This gating is enabled only when the LCP is in the "connected"state; when the LCP disconnects, the gating is disabled. The LCP is in a"connected" state when the LCP can transfer data between the IOT anditself. The "disconnected" state of an LCP is where the LCP isdisconnected from the IOT, but is now able to transfer data betweenitself and its peripheral unit.

In addition to the gated lines, there are some lines which are dedicatedto each individual LCP, for example, the line which goes from theDistribution Card to only one LCP. Those lines, which require no gating,are used for signals such as the LCP request for reconnection or the LCPaddress lines.

During the time an LCP is connected to the IOT, that LCP has theexclusive access to the Base Module Backplane. It is during this"connected" time that the IOT-LCP data transfer occurs. Upon cessationof the data transfers, the LCP disconnects from both the IOT and theBase Module Backplane, thus freeing them for use by other LCP's in thesysem. Once disconnected, the LCP is free to communicate, via thefrontplane, with its associated peripheral device, such as device 50.When a disconnected LCP requires that the connection to the IOT bere-established, that LCP sends a request signal, via one of itsdedicated backplane lines, to the Distribution Card, such as 20_(0d).Reception of the LCP request causes the Distribution Card to begin the"Poll Request" algorithm and to initiate the IOT Reconnection Module,10_(td), FIG. 5C.

Line Control Processor:

An LCP, Line Control Processor, is a device which is used as aninterface unit between a specific peripheral device and the Main System.The LCPs are made in a variety of types, each designed to operate with aspecific type of peripheral device. Since peripheral devices aredifferet in their operational characteristics, the LCP is devised tohandle, control and be particularly adaptable to its own specificperipheral device. However, there are certain general characteristics ofthe LCP interface unit which establish a common characteristic for allLCPs. Basically, the common characteristics of each LCP involve: theability to transform serial data to parallel data or to transformparallel data to serial data; to transform format from character toword-format, or to transform from word to character-format; to recognizeand take appropriate action in response to certain standard controlcharacters or signals.

A generalized block diagram of a Line Control Processor is shown in FIG.6B, which also indicates the relationship to Distribution Card Unit20_(0d) and IOT 10_(t). If the LCP is assumed to be in the "connected"state, and that a "write" operation has been initated, then data fromthe IOT 10_(t) enters the LCP through the backplane receivers 23_(r).Then the Multiplexor 24_(x1) is used to select the "data source" for theoperation, which in this case is the IOT 10_(t).

The output of Multiplexor 24_(x1) is bussed to both the LPW(longitudinal parity word) circuitry 24_(w) and also to the Multiplexor24_(x2), which gates the data from Multiplexor 24_(x1) into the databuffer 25₀₀. The LCP continues to receive data from the IOT 10_(t) untilthe data buffer 25₀₀ is filled.

In the period that the LCP is receiving data, the LPW circuitry 24_(w)is generating the LPW sum; then at the end of the transmission, the IOT10_(t) sends a longitudinal parity word LPW, (consisting of the"complement" of the transmitted word) which, if there were no errors inthe transmission "clears" the LPW circuitry 24_(w). If the circuitry24_(w) does not clear, then an error is indicated.

When the data buffer 25₀₀ is filled, the LCP disconnects from the MainSystem (IOT) by disabling its backplane transmitter drivers 23_(x) andbackplane receivers 23_(r) ; the LCP then establishes a data path to theperipheral device, such as 50, by enabling its frontplane transmitterdrivers 28_(x) and frontplate receivers 28_(r). Once this path isestablished, the LCP uses Multiplexor 27_(x) to select data (translatedor untranslated) from the data buffer 25₀₀ to be transmitted to theperipheral device 50. The transmission continues until the data buffer25₀₀ is empty, at which time the LCP requests a "reconnection" (to theIOT), either to store a Result Descriptor or to request more data.

If a "read" operation is in progress and the LCP is disconnected fromthe Main System (IOT), data from the peripheral devie 50 enters the LCPvia the frontplane receiver 28_(r). The output of the receiver 28_(r) isbussed to Multiplexor 24_(x1), which now selects the peripheral device50 (through frontplane receiver 28_(r)) as the "data source". The outputof Multiplexor 24_(x1) bypasss the LPW circuitry 24_(w) and goes on toMultiplexor 24_(x2), which selects Multiplexor 24_(x1) as the input tothe data buffer 25₀₀. When the data buffer 25₀₀ is filled, thefrontplane receivers 28_(r) and the frontplane drivers 28_(x) aredisabled, then the LCp reconnects to the IOT 10_(t), and the backplanereceivers 23r and backplane drivers 23_(x) are enabled.

The LCP now begins transmission (to the Main System 10) of the data fromthe data buffer 25₀₀, through the Multiplexor 27_(x) and driver 23_(x),over to the IOT 10_(t). During this transmission, the output ofMultiplexor 27_(x) also goes through the Multiplexor 24_(x1) over theLPW circuit 24_(w). When the data buffer 25₀₀ becomes emptied, the LCPsends a signal to the IOT 10_(t) indicating that the longitudinal parityword, LPW, is coming, after which it then gates the final LPW sumthrough Muliplexor 27_(x) and driver 23_(x) over to the IOT 10_(t).

After the transmission of the longitudinal parity word (LPW), the LCPmay either disconnect from the Main System (IOT) in order to receiveadditional data from the peripheral device 50, or, if there is nofurther data, the LCP may store a Result Descriptor and go on to an"idle" state.

In the above described operations, the informational data could havebeen transferred between the LCP and the peripheral device in the formof bits, characters, or words, depending on the type of peripheraldevice involved. The method of data transmission is typically controlledby the type of peripheral device used.

The above mentioned transmitter drivers 23_(x),28_(x) and the receivers23_(r),28_(r) are items kown in the art and are often called "tri-statebuffers". Such type of tri-state devices are desribed in a bookpublished by the Texas Instrument Company and entitled "TTL-Data Bookfor Design Engineers", 2nd edition, 1976. One typical tri-state bufferis designated as a "hex bus and driver with three state output".Likewise, the above mentioned multiplexors 24_(x1), 24_(x2) , 27_(x) arealso known in the art and described in the above mentioned data book fordesign engineers published by Texas Instrument Company. The use ofsimilar transmitters and receivers is illustrated in U.S. Pat. Nos.3,675,209, 3,680,055 and 3,975,712. The use of multiplexors is furtherillustrated by U.S. Pat. No. 3,408,632 and U.S. Pat. No. 3,972,030 and3,377,619.

Typically, the informational data is transferred between the LCP and theIOT 10_(t) as "words", with some instance of character transfers, as forexample, the first or the last character of a transmission. These datatransfers between the IOT 10_(t) and the LCP of FIG. 6B are controlledby the exchange of strobe pulses, and the recognition by the IOT 10_(t)of the LCP "status counts", to be described hereinafter.

As previously introduced in connection with FIG. 6A, the status count ofan LCP provides standardized information which is transmitted to the IOT10_(t) and which permits the IOT to take the next appropriate actionbased on the status count information.

During the time an LCP is "connected" to the Main System, it follows astandard communication procedure with the IOT 10_(t). Even though thesequence of events followed in the communication procedures may not beidentical for all LCPs, the particular events which occur at any onepoint in the sequence of communication procedure are all similar. Thesteps in the communication sequence, numbered 0 through 15, are called"status counts" and designated "STC". These status counts aretransmitted to the IOT 10_(t) which examines the status count (STC) eachtime it receives a strobe pulse from the LCP, and, based upon thatstatus count, the IOT can take appropratiate action.

Referring to FIG. 6A and the following table, it will be seen that eachstatus count has a particular function and further, depending on thetype of LCP and Descriptor involved, the status count will havedifferent exits. The following table VII briefly describes the variousLCP status counts:

                                      TABLE VII                                   __________________________________________________________________________    Status Count                                                                         Description                                                            __________________________________________________________________________    STC = 0                                                                              Master Clear                                                           STC = 1                                                                              Disconnect. The LCP is communicating                                          with it's peripheral device.                                           STC = 2                                                                              Not Ready. The LCP is idle. The Peripheral                                    device is not ready. The LCP can receive                                      descriptor information from the System.                                STC = 3                                                                              Ready. The LCP is idle. The peripheral                                        device is ready. The LCP can receive                                          descriptor information from the System.                                STC = 4                                                                              Read. The LCP transmits data from its buffer                                  to the System.                                                         STC = 5                                                                              Send Descriptor Link. The LCP sends the                                       Descriptor Link to the IOT in order to re-                                    establish connection.                                                  STC = 6                                                                              Receive Descriptor Link. The LCP receives the                                 Descriptor Link from the IOT during the IOT                                   "connection" sequence.                                                 STC = 7                                                                              Result Descriptor. The LCP transmits its                                      Result Descriptor to the IOT                                           STC = 8                                                                              Write. The LCP receives data from the System.                          STC = 9                                                                              Encoded Status. One character transmitted;                                    LCP sets D1 bit (FIG. 4C Result Descriptor) as                                a flag to the IOT. The IOT decrements the                                     address by 2.                                                          STC = 10                                                                             Write One More Word. The LCP data buffer                                      can hold only one more word.                                           STC = 11                                                                             I/O Descriptor LPW. The LCP receives and                                      checks the LPW for the I/O Descriptor received                                in STC = 2 or STC = 3. The I/O Descriptor,                                    after being translated by the IOT, then becomes                               known as the Command Descriptor.                                       STC = 12                                                                             Break. There is no more data to be                                            transferred. The LPW, is transmitted                                          and checked.                                                           STC = 13                                                                             Break Enable. Data transfer has been                                          halted; the LCP is requesting a return                                        to STC = 8 (Write) or to STC = 4 (Read).                               STC = 14                                                                             Character Transfer. The last transmission                                     consisted of a character instead of a                                         word.                                                                  STC = 15                                                                             Result Descriptor LPW. The LCP sends                                          the LPW for the Result Descriptor to the                                      IOT.                                                                   __________________________________________________________________________

Referring to FIG. 5C, the Processor 10_(p) starts the chain ofinput-output operations by the execution of an Initiate I/O instruction.In this situation, the Processor passes certain information, includingthe channel number of the desired LCP over to the IOT Initiation Module10_(ta) of FIG. 5C. The channel number is decoded to determine the BaseModule number and the address of the LCP, which are then passed over tothe Connection Module 10_(tb). The Connection Module then selects theproper LCP Base Module and sends a signal (channel select) to theappropriate Distribution Card, as 20_(0d), for that Base Module, as 20₀,requesting that a connection attempt be made. The above describedoperation is called a "Pool Test" and is a means for the Main System toseek connection to an LCP; it is, further, a method by which theDistribution Card 20_(0d), in response to the connection request, alsoattempts to connect to a specific LCP.

Following the transmission of a "Channel Select", the IOT 10_(t) sendsthe address of the desired LCP to the Distribution Card in the selectedBase Module. At the same time, the IOT sends "Address Select" to allBase Modules in the system. The Distribution Card that receives both theAddress Select and Channel Select begins a "Poll Test" and responds tothe IOT with an "LCP Strobe"; the Distribution Cards that received theAddress Select only, consider it as a "busy" signal, and they areinhibited from communication with the IOT. When the IOT 10_(t) receivesthe LCP Strobe, it drops the Channel Select.

When the Distribution Card receives an "Address Select" and "ChannelSelect", a signal is generated which enables the LCP address to beplaced into an LCP address register in the Distribution Card. The BCD(Binary Coded Decimal) output of the LCP address register is decoded toenable one of eight lines. Each line represents one LCP in the BaseModule. When an LCP detects that its address line is active, then thtLCP responds to the Distribution Card with the signal LCPCON meaning"LCP connected". When this connected signal is received in theDistribution Card, a connect flip-flop (CONF) is set. Then depending onthe state of the I/O send line (ISOND/ FIG 6C) from the connected LCP,this will cause an activation of control lines for either receiving dataor sending data as between the LCP and the IOT (FIG. 6C).

If a Distribution Card detects the absence of Channel Select, itresponds to the IOT with the LCP's status, accompanied by a strobe. TheLCP is now connected to the IOT and remains connected until the IOTdrops Address Select; the Distribution Card takes no further part in theIOT-LCP communications.

The above events show the steps leading to a successful "connection"attempt; however, the connection attempt could have failed due to one ofthe following causes;

(a) there was no LCP at the location addressed or the LCP at the addresslocation was off-line;

(b) the LCP was busy, that is the LCP status count was not 0 or 2 or 3;

(c) the port was busy, that is, a second Distribution Card in the BaseModule was busy;

(d) a parity error was detected in the address.

The detection of any of these errors would cause the connection attemptto be aborted and a Result Descriptor indicative of the type of failureto be written and sent to the Main System in 10_(mr) of Memory 10_(m)(FIG. 3).

In subsequent discussions, reference may occasionally be made tospecific flip-flops and signal levels which are not specifically shownwithin the block diagrams. Since the design and use of such elements arewell known, it is considered to be redundant and overcomplex to show allsuch elements.

Poll Request:

An LCP, after having been connected to the IOT 10_(t) and receiving theCommand Descriptor and the Descriptor Link, may "disconnect" from theMain System 10 in order to communicate with its associated peripheraldevice, such as 50. If that LCP subsequently requires access to Memory10_(m) , it sends a request (LCPRQ) over to the Distribution Card. The"Poll Request" is the method by which the Distribution Card, in responseto the LCP's request, attempts to reconnect the LCP to the IOT. A numberof events occur during a "Poll Request" operation.

If several LCPs within the Base Module 20₀ simultaneously requestaccess, the Distribution Card 20_(0d) determines which one of them is togain access by checking their priority levels; thus, the requesting LCPwhich has the highest priority level (this priority selected atinstallation time) is given access to the Distribution Card. Thispriority level is called "Base Priority" as it involves which LCP haswhat level of priority as among the eight LCPs residing in thatparticular Base Module.

Once the "Base Priority" is resolved, the Distribution Card assigns a"Gobal Priority" (which has also been assigned and selected atinstallation time) to the requesting LCP. The "Global Priority"establishes the priority rank between different Base Modules in theoverall system rather than just the priority rank of LCPs in one singleBase Module.

The Distribution Card 20_(0d) contains a series of pins or socket-typeconnections which are connected to each individual LCP. These pin-socketconnections can be jumpered (by a field engineer) to a priority encoderwhich assigns an internal base priority number from zero (low) to seven(highest) to each LCP. Thus, if several LCP's in the same Base Modulerequest connection concurrently, then the Distribution Card controlmeans will put through the LCP with the highest priority.

Another set of pin-sockets on the Distribution Card are connected toeach LCP. These are "jumped" or "strapped" by a field engineer so thateach LCP is given a "global" or external priority number to permit theInput/Output Translator interface of the Main System to select amongstLCP's which reside in different Base Modules of the system. Thus, whenthe "global" priority number is received by the IOT, and there areconcurrent requests from other LCP's in other Base Modules, the IOT willselect the LCP with the highest global priority number, but this occursonly after internal base priority has been resolved by the DistributionCard.

Those Distribution Cards receiving requests from their associated LCPs,each send an "Interrupt Signal" (IP+ST4) over to the IOT 10_(t). (Seemessage level interface FIG. 5E and Table VI). When the IOT 10_(t)detects the signal IP+St4, it begins the "reconnection" sequence andsends a signal (Access Granted) to all the Base Modules in the system.The "Access Granted" signal causes those Distribution Cards that sentthe IP+ST4 to the IOT 10_(t) to being their individual "Poll Request"algorithms.

In response to the "Access Granted" signal, the requesting DistributionCards send their individual Global Priorities over to the IOT 10^(t),The IOT compares the Global Priorities of the requesting DistributionCards (that is, sends the Channel Select signal over to the requestingDistribution Card which has the highest Global Priority one clock-timelater) and the IOT sends an Address Select signal to all DistributionCards in the system. The Distribution Card that receives both the"Channel Select" and the "Address Select" responds to the IOT with theLCP Strobe, then sets its LCP Address flip-flop, thus driving thespecific address line of the requesting LCP. When the LCP detects thatits own address line is active, it then responds to the DistributionCard with the LCP connected signal (LCPCON).

Upon receipt of the LCP Strobe, the IOT 10_(t) drops "Access Granted"signal and the "Channel Select" signal; and when the Distribution Carddetects the absence of the "Access Granted" and the "Channel Select" anddetects the presence of LCPCON, it then assumes a connection to becompleted and responds to the IOT with an LCP strobe, accompanied by theLCP Status Count and the Descriptor Link.

The Poll Request is now complete; the Distribution Card takes no furtherpart in the LCP-IOT communication. The LCP and the IOT continue with thereconnection sequence until the LCP is connected, after which control ispassed to the I0T Data Transfer Module 10_(tc), FIG. 5C. The LCP remainsconnected until the time when the I0T drops its "Address Select" signal.

Error Checks:

Each transmission between the IOT and a particular LCP is checked forerrors. The error checking methods used are (a) vertical parity checkingon each word transmitted, and (b) longitudinal parity checking on eachblock transmitted.

(a) Vertical Parity:

In "Read" operations, the LCP sends information to the IOT 10_(t) on 16message level interface (MLI) data lines, (FIG. 5E) accompanied by theparity bit on the MLI parity line, FIG. 5E. The data and parity lines goto a parity generator-checker on an IOT base driver card. In "Read"operations, the parity generator checker is used to count the number of1-bits on the MLI data and parity lines. If the total number of 1-bits(including the parity bit) is odd, then parity is correct and a signalterm (PAROK, FIG. 6D) from parity-generator 48 is generated. If thetotal number of one bits is even, then the PAROK signal is notgenerated; the absence of PAROK at the time that data is received,caused the I0T to set a vertical parity error flip-flop (VPERRF).

Similarly, in "Write" operations the 16 data lines from the Main System10 are bussed to a parity generator-checker on the I0T base driver card.The data on the 16 lines is examined and if an even number of 1-bits isdetected, the term PARGEN is generated. This PARGEN signal is then usedto force a "1" bit onto the message level interface parity line toaccompany the data to the LCP. On the LCP Base Distribution Card, thestate of the parity bit controls the parity generator-checker circuit.The parity generator-checker circuit examines the states of the 16 datalines and generates PAROK if the total number of 1-bits, includingparity, is odd.

(b) Longitudinal Parity Checking:

Longitudinal parity checking is an error detection method in which acheck word generated by a sending unit is compared to a check wordgenerated in the same manner by a receiving unit. These check words aregenerated by treating each word in the transmission as a 16-bit number,then performing an exclusive OR operation (binary addition withoutcarry) of each word in the transmission. At the end of the transmission,the sending or transmitting device sends the check word it has assembledover to the receiving device. If there have been no errors in thetransmission, the addition of the check word from the transmittingdevice to the check word in the receiving device results in a sum of"0". Thus, if the sum is not "0", a longitudinal parity error flip-flopis flagged (LPERRF).

As was discussed in connection with FIG. 6B, the LCP was provided withLPW circuitry 24_(w). Likewise, there is longitudinal parity checkingcircuitry in the IOT 10_(t). This circuitry connects in a parallel pathto the data bus shown as the lower 16 lines of FIG. 5E.

The Line Control Processor (LCP), such as element 20₀₀, may be betterunderstood with reference to FIG. 6C which represents a basic blockdiagram of the major elements involved in addition to some specificdetails with regard to the RAM buffer such as 25₀₀ of the LCP, 20₀₀.

The LCP buffer 25₀₀ is a random access memory (RAM) which isfunctionally 256 bits (0-255) wide and 18 bits deep. It can thus hold256 words of 18 bits each. In one typical embodiment, the buffer 25₀₀may have a section designated buffer A, 25_(a), having provision for 90longitudinal words of 18 bits each; another section designated 25_(xi) ;a Command Descriptor C/D section designated 25_(c) ; a buffer area B,25_(b) which may typically be 90 words long, (i.e., from address 128over to address 218); another buffer area designated 25_(x2) ; a ResultDescriptor R/D area 25_(r) ; another area designated 25_(x3) ; and aDescriptor Link D/L area designated 25_(d).

The RAM buffer 25₀₀ is addressed by a memory address register 36 havinga system address register section 36_(s) and a device address registersection 36_(d), which communicate to the buffer 25₀ via an eight-bitaddress bus, B₈. The RAM buffer 25₀₀ is functionally composed in thevertical direction (FIG. 6C) of 16 bits plus a parity bit, plus aneighteenth bit called an "end flag bit", the end flag bits residing in astorage section designated as 25_(e).

A "data bus" 47 provides a data input and output channel for the buffer25₀₀ to communicate to the Main System 10 through the system interfacelogic 22_(si) ; and for the buffer 25₀₀ to communicate to its peripheralunit via a device interface 22_(di). The system interface logic 22_(si),the device interface logic 22_(di), and the common logic 22_(c)schematically represents blocks which refer to more specific elementswhich are described in connection with FIG. 6D.

As will be later discussed, the system interface 22_(si) would includethe logic functions which generate the result descriptor and the logicfunctions which decode and execute the operands including (FIG. 6B)transmitter and receiver 23_(x1), 23_(r), the multiplexors 24_(x1),24_(x2) and standard clocking logic for the signal lines between datamemory buffer 25₀₀ and the Distribution Card 20_(0d). The deviceinterface logic 22_(di) would include logic circuitry for paritychecking and logic to transfer data between the peripheral device to thedata buffer and thence to the Main System. The system interface logic22_(si) would properly include the (FIG. 6D) elements of the STCregister 53 and its decoder 54 plus the input multiplexor 24_(x1) andthe bi-directional lines B_(i). The device interface logic 22_(di) wouldinclude the universal asynchronous receiver transmitter (UART) 31 andthe UART multiplexor 27_(x) (FIG. 6D).

Referring to FIG. 6F, there is shown a "message block" of the type usedin the LCP buffer 25₀₀ of FIG. 6C.

As mentioned with the discussion of FIG. 6C in regard to the RAM buffer25₀₀, this is typically a message block of "n" words, which blockprovides 90 words (or n=90) for data storage; and also there may beprovided three words for Result Descriptors R/D; there may be providedthree word locations for Command Descriptors C/D; and there may be oneword location for Command Messages C/M.

FIG. 6F also shows the basic word format, in that a word is composed offour digits which are: A, B, C, and D plus a parity bit marked VPB(vertical parity bit), which normally makes a total of 17 bits per word.

As seen in the drawing of FIG. 6F, the four digits A, B, C and D areeach made up of four bits designated as the "8" bit, the "4" bit, the"2" bit, and the "1" bit.

In FIG. 6C, the buffer 25₀₀ is also provided with an 18th bit or "endflag" bit which is placed in the location designated 25_(e) of FIG. 6C.

The central or Main System 10 communicates with the peripheral terminalunit via the LCP. The LCP provides the means for transferring controlinformation and data from the Main System 10 to the peripheral terminalunits, such as 50, and vice-versa. The LCP looks at the CommandDescriptor C/D received from the Main System 10 and sets itself up toperform the operation required if it is sensitive to that particularcommand. It also transfers the same Command Descriptor C/D unmodified tothe peripheral terminal unit. The peripheral terminal unit acts upon theCommand Descriptor C/D and returns Result Descriptors R/D to the MainSystem 10 via the LCP. The message block and the word formats have beenshown in FIG. 6F. Typical Command Descriptors C/D and Result DescriptorsR/D will be shown subsequently hereinafter.

The LCP accepts the Command Descriptor C/D transmitted by the MainSystem 10. The C/D contains a digit of the OP code, 3 digits ofvariants, and 6 digits of C address. The Command Descriptor C/D isreceived by the LCP via 4 digits per transmission for a total of 3 words(4 digits per word). The two least significant digits contain all zeros.With each word there is a vertical parity bit (VPB) and the entire C/Dis followed by a longitudinal parity word (LPW). Should a parity errorbe detected on transmission of the C/D, the LCP will branch to a ResultDescriptor R/D mode and report a descriptor error to the Main System 10.

The random access memory buffer 25₀₀ (RAM of the LCP) buffers the entireCommand Descriptor, the vertical parity bit and the longitudinal parityword within the LCP, Line Control Processor.

The LCP examines the first word of the Command Descriptor C/D anddetermines whether it is an ECHO OP, HOST LOAD OP, or READ NO timeoutOP. If it is one of these, it sets the appropriate flag.

Descriptor Link (D/L):

Following the receipt of the Command Descriptor C/D, the Line ControlProcessor LCP proceeds to accept the Descriptor Link D/L. This is a twoword transmission followed by a longitudinal parity word LPW. Shouldthere be an error, the LCP branches to the Result Descriptor R/D mode,and reports a descriptor error to the System 10.

The random access memory RAM of the buffer (such as 25₀₀) acts as thebuffer for the entire Descriptor Link D/L, the vertical parity bit (VPB)and the longitudinal parity word LPW.

Disconnect Mode:

Following the receipt of the Descriptor Link D/L, the LCP goes to the"disconnect mode".

Reconnect Mode:

If it is an ECHO OP, the Line Control Processor LCP proceeds to"reconnect mode" and starts operating on the ECHO OP which involves thereceiving of two buffers of data (each 180 bytes, or 90 words of 16bits) and the transmitting of the same data back to the System Memory10_(m).

If it is other than an ECHO OP, the LCP examines the readiness of theperipheral terminal unit. Should the peripheral device be in the"not-ready" state, the LCP branches to the Result Descriptor R/D modeand reports this to the System 10.

If the peripheral device is "ready" the LCP starts communicating theCommand Descriptor C/D to the peripheral device, while at the same timebranches to the "idle" state to make itself available for a possible"Conditional Cancel OP". The Line Control Processor LCP stops in this"idle" state until one of two things happen:

1. The peripheral device sets up the Line Control Processor LCP to a"data transfer" state.

2. The System 10 communicates a "Conditional Cancel OP" or anUnconditional Cancel.

If it is number 2 above, the Line Control Processor LCP accepts one wordfrom the System 10 followed by the longitudinal parity word LPW, and theLCP determines if it is a valid Conditional Cancel OP. In any case theLCP communicates this to the peripheral device. If the situationinvolves number 1 above, the LCP branches back to the "disconnect"state, where data transfer between the LCP and its peripheral can occur.

After transmission of the Command Descriptor C/D to the peripheral, theLCP is driven by the peripheral device "state", which defines theoperation mode and the memory requirements. Data is transferred in"message blocks" together with a longitudinal parity word (LPW) of 16bits following each block and with a parity bit on every word (except ina disk pack controller situation, the message block would consist of asegment). If the Line Control Processor LCP detects an error on datareceived from the peripheral device or from the Main System 10, itreports this information to the peripheral device and then branches tothe Result Descriptor R/D mode and reports it to the Main System 10.

In the "Read" mode, the data transfer between the Line Control ProcessorLCP and the peripheral device is dependent on the requirements of theperipheral device. On the other hand, data transfer between the LCP andMain Memory 10_(m) is dependent upon the memory access rate of the MainSystem 10. Since the Peripheral device may operate in a "stream" mode,and the LCP must compete with other LCP's for access to memory, the LCPalternates between its two buffer areas to accommodate the transfer rateof the peripheral device.

Table VIII below indicates certain types of Command Descriptors C/Dwhich are used and acted on by the LCP. All other C/D's are transparentto the LCP and pass through to the peripheral device:

                  TABLE VIII                                                      ______________________________________                                        Command Descriptors                                                           The LCP is transparent to all Command Descriptors except                      for the following as determined by testing the first word                     of the C/D:                                                                   1. ECHO OP            (bit Al is true)                                        2. HOST LOAD          (A4 and B8 are true)                                    3. READ NO T/O (timeout)                                                                            (A8 and B8 are true)                                    4. CONDITIONAL CANCEL OP                                                                            (A2 and B8 are true).                                   5. UNCONDITIONAL CANCEL                                                       OP code digits of the C/D are defined as follows:                             Read (A8) -                                                                              Any operation where data is transmitted                                       from the LCP buffer to the Main System.                                       (1000)                                                             Write (A4) -                                                                             Any operation where data is transferred                                       from Main System Memory to LCP buffer.                                        (0100)                                                             Test (A2) -                                                                              Any operation where no data transfer                                          takes place between LCP and System                                            Memory but results in a R/D storage                                           in System Memory. (0010)                                           Echo (A1) -                                                                              Operation that results in receiving a                                         message block from System Memory and then                                     transmitting the same block back to System                                    Memory. (0001).                                                    ______________________________________                                    

Normally Result Descriptors R/D are generated by the peripheral unit andaccepted by the LCP in one, two or three words. When the LCP generates aR/D, only one word is sent to the Main System 10. Table IX shows theconditions for the LCP to generate a Result Descriptor:

                  TABLE IX                                                        ______________________________________                                         Result Descriptors                                                           Bits        Condition                                                         ______________________________________                                        A8          Not Ready                                                         A4          Descriptor Error                                                  A2          System Vertical Parity Error                                      A1          System LPW Error                                                  B8)         Time-Out                                                          B4          Remote Device Vertical Parity Error                               B2          Remote Device LPW Error                                           B1          (blank)                                                           ______________________________________                                    

Referring to FIG. 6C with respect to the lines between the deviceinterface 22_(di) and the peripheral unit, the peripheral device unitmay be provided with a port interface which may be designated as a DDPor device dependent port interface, 50_(d), which is tailored to therequirements of each specific type of peripheral device.

The LCP communicates to the peripheral via the DDP in an asynchronousmode. The "Write" operation is defined as a transfer where the LCP iswriting into the peripheral device unit. The "Read" operation is definedas a transfer where the LCP is reading from the peripheral device unit.

Referring to FIG. 6C the line marked HTCL/ may be designated as the HostTransfer Control Level, and when the LCP "Writes" into the peripheraldevice unit, this signal is the asynchronous level, which signifies thepresence of data on the data lines. This level is de-activated by theperipheral unit sending DML/ (peripheral message level) or by sendingDINTL/ (peripheral device interrupt level) to the LCP.

When the LCP is "Reading" data on a Result Descriptor R/D from theperipheral unit, this HTCL/ signal is the asynchronous acknowledgementthat the data on the data lines has been received by the Line ControlProcessor LCP. Upon receipt of this level, the peripheral device unitmust deactivate DML/ or DINTL/. When the peripheral unit causes thede-activation of DML/ or DINTL/, then the LCP de-activates HTCL/ (theHost Transfer Control Level).

When the peripheral device unit drives the LCP to the Command MessageC/M mode, the Host Transfer Control Level HTCL/ is sent to theperipheral device unit when the LCP's buffers are empty and no systemterminate has been detected. The HTCL/ must be answered by theperipheral device unit with a DINTL/ and a change-of-state.

The line in FIG. 6C marked HINTL/ is designated as the Host InterruptLevel and is used by the LCP to indicate to the peripheral unit that theLCP wishes to interrupt the operation. The response to this level by theperipheral device must be DINTL/ and a change-of-state, to which the LCPresponds by de-activating its Host Transfer Control Level, HINTL/.Following the detection of the trailing edge of HINTL/, the LCP willrespond to the new mode of operation described by the state line shownon FIG. 6C as ST-4/, ST-2/, ST-1/.

When an interrupt from the System 10 is activated in the "Write" mode,the Host Interrupt Level HINTL/ signifies that the last word of data hasbeen transmitted and the LPW is on the data line of bus 47. Theperipheral unit needs to respond to the interrupt with a DINTL/ and achange-of-state.

In the "Read" mode when the LCP detects the "Read Terminate" command,the LCP will activate the Host Interrupt Level HINTL/. In the CommandMessage C/M mode, the LCP will activate the Host Interrupt Level HINTL/if a "Read Terminate" has been detected.

The line of FIG. 6C designated HCL/ refers to "Host Clear" whichindicates to the peripheral unit that the LCP is being cleared by theMain System 10, or that a parity error has occurred during a read.

A combination of the Host Transfer Control Level and the Host InterruptLevel (HTCL/ - HINTL/) indicates to the peripheral unit the presence ofa Host Load Command Descriptor C/D. The peripheral unit responds byactivating the line marked DINTL/ (peripheral interrupt level) and theStatus Count ST=2; the LCP acknowledges by de-activating both levels ofHTCL/ - HINTL/. Following the trailing edge of DINTL/, the LCP transfersdata in the "Write mode".

In FIG. 6C a bidirectional data bus B_(d) is provided having 16 datalines and a parity line between the LCP and the peripheral unit. Whencontrolled by the LCP, these lines are active as long as the HostTransfer Control Level HTCL/ is active. When control is held by theperipheral unit, these lines are active as long as the peripheral devicemessage level DML/ is active. The direction of transfer is determined bythe status of the peripheral unit. The line designated DML/ refers tothe peripheral device message level and is a unidirectional line. Whenthe LCP is reading data or a Result Descriptor R/D from the peripheralunit to the LCP, the peripheral device message level DML/ is used as atransit signal to indicate the presence of stable data on the datalines. When the peripheral device receives a CommandDescriptor C/D ordata from the LCP, this signal, DML/, is used as an acknowledge levelfor data.

The peripheral device (via its port interface) uses the DINTL/(peripheral interrupt level) to request the LCP to change its mode ofoperation. This is done by activating DINTL/ and presenting the properstate on the state lines, ST-4/, ST-2/, ST-1/. The state lines must bestable during the time that DINTL/ is active.

In the "Write Mode":

DINTL/ is the acknowledge level to the Host Transfer Control Level HTCL/and the LPW data word; or else it is the response to HTCL/ or HINTL/ inthe Command Message C/M mode. DINTL/ will cause a change-of-state tooccur for either the above. When the LCP is writing into the peripheralunit, the peripheral device interrupt level DINTL/ is based on theleading edge of HTCL/ or HINTL/. DINTL/ is de-activated by the trailingedge of these signals (HTCL/ - HINTL/).

In the "Read Mode":

The peripheral interrupt level DINTL/ is a no-data transfer "strobe"used exclusively to change states, DINTL/ is acknowledged by the HostTransfer Control Level HTCL/ in the Read Mode. When the LCP is readingfrom the peripheral device unit, the peripheral device activates DINTL/instead of the peripheral message level DML/, and de-activates DINTL/when the peripheral unit detects the leading edge of the Host TransferControl Level HTCL/.

In the Host Load Mode:

This mode involves the transfer or loading of data from the peripheraldevice, as 50, FIG. 6C, into the LCP (Host) for the "Read Mode" and viceversa for the "Write Mode".

The peripheral device interrupt level DINTL/ is the acknowledge level toHTCL/ - HINTL/ as the Host Load Command. The peripheral device activatesDINTL/ and changes to State 2 (Table X). The LCP acknowledges this byde-activating both HTCL/ - HINTL/, and if in the "Write Mode", startswriting into the peripheral device memory. To interrupt this mode theperipheral device unit 50 activates DINTL/ in the same manner as in aregular "Write Mode".

The "State" lines:

In FIG. 6C, these unidirectional lines ST-4/, ST-2/, ST-1/, indicate tothe LCP the state of the peripheral device, and from this, the LCPdetermines what kind of operation mode is required. For example, in atypical embodiment, there may be eight states, 0-7, as seen in Table X,for the peripheral device which might be used to indicate the followingconditions: peripheral device not on-line; Read operations; Writeoperations; Result Descriptor; Command Message (C/M); reset LCP timer(RT); ready or writing Command Descriptor (C/D); last word of a block orthe Result Descriptor and longitudinal parity word (R/D-LPW) is next tobe transmitted.

A typical coding system for the state lines from a typical peripheraldevice unit is shown herein below in Table X:

                                      TABLE X                                     __________________________________________________________________________    State Lines                                                                   ST=                                                                              ST-4/                                                                             ST-2/                                                                             ST-1/                                                                             Condition   Data Line Direction                                __________________________________________________________________________    0  0   0   0   Peripheral Device                                                             Not On Line                                                    1  0   0   1   Read        From    Peripheral Device                          2  0   1   0   Write       To      Peripheral Device                          3  0   1   1   R/D         From    Peripheral Device                          4  1   0   0   Command Message                                                                           No Data Xfer                                       5  1   0   1   Reset HD Timer (RT)                                                                       No Data Xfer                                       6  1   1   0   Ready or Writing C/D                                                                      To      Peripheral Device                          7  1   1   1   Last Word of a Block or                                                                   To or From                                                                            Peripheral Device                                         R/D-LPW is next                                                __________________________________________________________________________

The interface discipline between the LCP and the peripheral device unitvia the peripheral device unit port interface (DDP 50_(d), FIG. 6C) mayagain be locked at in terms of a "Reading Mode" and a "Writing Mode".

Reading Mode:

with the Line Control Processor LCP reading from the peripheral deviceunit (State=1+7), the peripheral device unit (as 50, FIG. 6C) places aword on the data lines and activates the peripheral device message levelDML/. The LCP acknowledges this by activating the Host Transfer ControlLevel (HTCL/). The peripheral device unit now de-activates DML/, andthen the LCP de-activates the HTCL/. This process continues in State=1until:

1. The LCP activates the Host Interrupt Level (HINTL/). The peripheralunit acknowledges by de-activating the peripheral message level (DML/),if active, and activates the peripheral device interrupt level (DINTL/)with a change-of-state. This indicates to the peripheral device that theLCP has a "Command Message" C/M to send to the peripheral device.

2. The peripheral device activates the peripheral device interrupt levelDINTL/ instead of the peripheral message level DML/, with the properchange in the State Lines. The LCP acknowledges by activating the HostTransfer Control Level (HTCL/), and, following the de-activation ofDINTL/, it de-activates the Host Transfer Control Level HTCL/ and goeson to the proper State. DINTL/ does not transfer data on the data lines.

3. When the peripheral device detects it is transmitting the Last Wordof a block, the peripheral device changes to Status ST=7 with theleading edge of DML/. The LCP answers the peripheral device with a HostTransfer Control Level (HTCL/) and expects the next transfer to be thelongitudinal parity word LPW. The LPW is transmitted with the peripheralmessage level DML/ and answered with a Host Transfer Control Level(HTCL/).

4. If the LCP detects a vertical or longitudinal parity error, the LCPwill not acknowledge the peripheral message level DML/ from theperipheral device. Instead the LCP will generate a Host Clear Level(HCL/).

In the Writing Mode:

If the LCP is writing data into the peripheral device (State=2+7), thefollowing actions take place:

The LCP places a word on the data lines and activates the Host TransferControl Level (HTCL/). The peripheral device acknowledges by activatingthe peripheral device message level (DML/). The LCP now de-activates theHost Transfer Control Level (HTCL/), and then the peripheral devicede-activates the peripheral message level (DML/).

This process continues (Table X) in Status ST=2 until:

1. The peripheral device changes state to ST=7, then activates theperipheral message level DML/ which flags the LCP that the Last Word ofthat block has been received. The next word in the data lines must be alongitudinal parity word LPW when the Host Transfer Control Level HTCL/becomes active again. Then the peripheral device activates theperipheral interrupt level DINTL/ instead of the peripheral devicemessage level DML/, accompanied by a change in the State Lines.

2. At ST=2 or ST=7, the LCP activates the Host Interrupt Level HINTL/instead of the Host Transfer Control Level HTCL/. In this mode, HINTL/signifies an interrupt and that a longitudinal parity word LPW is on thedata lines. The peripheral device acknowledges by activating theperipheral interrupt level DINTL/ and a change-of-state. The LCPde-activates the Host Interrupt Level HINTL/ and goes to the proper modeafter DINTL/ is de-activated.

In another mode called the "Result Descriptor R/D Mode", the LCP reads aResult Descriptor R/D from the peripheral device (State=3+7). When inthe R/D Mode, the LCP is reading the Result Descriptor on the data linesfrom the peripheral device. The Result Descriptor R/D can be from 1 to 3words long plus a longitudinal parity word LPW. The first and secondwords of the 3-word Result Descriptor R/D are read in Status ST=3. Thelast word of the Result Descriptor R/D is read in Status ST=7. Theperipheral device message level DML/ signifies there is stable data onthe data lines. Each Result Descriptor R/D word transferred is thenacknowledged with a Host Transfer Control Level HTCL/. If a 1-wordResult Descriptor R/D is received by the LCP, then data transfer occursafter going from Status ST=3 to Status ST=7 together with a peripheraldevice message level DML/ which signifies a 1-word Result DescriptorR/D. The next word on the data lines is the R/D longitudinal parity wordLPW which is strobed by the peripheral device message level DML/. Afterthe LCP finishes reading a complete Result Descriptor R/D together withits appropriate longitudinal parity word LPW, the peripheral devicereturns to Status ST=6. It can now accept a Command Descriptor C/D.

Command Message C/M Mode:

This involves the situation in which the LCP is writing a CommandMessage into the peripheral device (State ST=4). When the LCP is in the"Read" mode and is directed to the Command Message C/M mode(DINTL/+ST=4), the LCP continues to send data to the Main System 10until:

1. The "read-system terminate" is detected which results in activatingthe Host Interrupt Level HINTL/ or:

2. Data buffer areas A and B (of buffer 25₀₀, FIG. 6C) are empty and the"read-system terminate" is not detected. This causes the LCP to activatethe Host Transfer Control Level HTCL/, indicating that the Main System10 expects more data.

The Reset Timer (R/T) Mode:

This occurs when the peripheral device resets the LCP time (State ST=5).A change-of-state to ST=5 resets the LCP timer. This change-of-stateoccurs without a strobe. The peripheral device unit must remain in ST=5for at least 500 nanoseconds.

The Send Command Descriptor (C/D) Mode:

In this case the LCP is writing a Command Descriptor C/D into theperipheral device (State=6). In this send Command Descriptor Mode C/D,the LCP writes 3-words followed by a longitudinal parity word LPW. TheHost Transfer Control Level HTCL/ that accompanies the C/D and LPW isacknowledged by the peripheral device interrupt level DINTL/ and achange to the proper state.

The Last Word of Block Mode:

This is the State=7 (of Table X) and during a "Read" operation withST=7, the LCP is reading the last word of a block of data (or else aResult Descriptor R/D) from the peripheral device. The next word will bean LPW. During a "Write" operation with ST=7, the LCP is writing thelast word of a block into the peripheral device. The next word will be alongitudinal parity word LPW.

Conditional Cancel:

After the LCP writes the Command Descriptor C/D into the peripheraldevice unit and before the peripheral device changes from Status ST=6with the peripheral interrupt level DINTL/, the Main System 10 canterminate the operation (OP) by issuing a "Conditional Cancel". In thiscase, the LCP de-activates the Host Transfer Control Level HTCL/ andthen activates the Host Interrupt Level HINTL/ as long as the StatusST=6 and DINTL/ is not active.

Unconditional Cancel:

The Main System 10 can generate an "Unconditional Cancel". This causesthe LCP to generate the Host Clear Level HCL/ to the peripheral device.No acknowledgement is required from the peripheral device.

The LCP (Line Control Processor) Subsystem consists of a number ofindividual LCPs which communicate to the Main System 10 through the IOT10_(t). While each of the several LCPs have basically the same designand provide the same basic system functions, there are variations of aminor nature as between the various types of LCPs, since each LCP istailored to meet the operational requirements of the particularperipheral terminal unit that it services.

The discussion following herein will involve an operational descriptionof one preferred embodiment of a particular LCP which is provided for aperipheral terminal unit known as the "Supervisory Terminal".

The necessary functional elements of the LCP include registers,counters, encoders, decoders, busses, logic elements, etc. In additionthere is a large scale integrated (LSI) receiver/transmitter forimplementing communication between the LCP and its peripheral terminalunit. Within the LCP, there are functionally two divisions that are usedfor communication between the LCP and the Main System 10. They aredesignated as the "read module" and "write module". These modules exist"functionally", but they are not separate components, since many of thelogic levels of which they are composed are shared by both modules. The"read module" is used to transfer data from the LCP over to the MainSystem 10, and is active when the transmit flip-flop (XMITF) in the LCPis set. The "write module" is used to transfer data from the Main System10 over to the LCP, and is active when the receive flip-flop (RECVF) isset.

Functionally, the components of the LCP are contained in three majorsections: (A) Terminal Control; (B) Data Flow; and (C) System LogicSection. In order to understand the means by which the LCP communicateswith the Main System 10 and with the associated peripheral terminalunit, such as 50, the functional characteristics of the followingcomponents will be discussed:

A. Peripheral Terminal Control Section

1. Universal Asynchronous receiver/transmitter (UART).

2. UART Multiplexor.

3. Block check character register (BCCR).

4. Block check character decoder.

5. End code decoder.

6. Memory address register.

B. Data Flow Section

1. Input Multiplexor

2. OP code register.

3. Variant register.

4. Valid OP encoder.

5. LCP buffer (RAM).

6. Terminal bus multiplexor.

7. Terminal bus.

8. Vertical parity generator/checker.

9. Data Latch register.

10. Longitudinal parity word (LPW) register.

11. LPW encoder.

12. End code decoder.

C. System Logic Section

1. Status Count (STC) register.

2. STC decoder

The above mentioned functional components will be understood withreference to FIGS. 6B, 6C, 6D, 6E, and 6F, with particular references toFIG. 6D.

Examples of types of interconnections between peripheral devices and I/Ointerface units may be found in U.S. Patents, such as Nos. 3,510,843;3,514,785; 3,526,878. Examples of the circuitry involved incommunication between remote units and corresponding buffer registers ina typical fashion can be found by reference to U.S. Pat. No. 3,390,379.

With reference to FIG. 6D and the Peripheral Terminal Control (SectionA) previously mentioned, the universal asynchronous receiver transmitter(UART) 31 is used as the interface between the asynchronous serial datachannel of the terminal unit device interface 22_(di) and the paralleldata transmission channel of the LCP. The transmitter section of theUART 31 converts a parallel data character and the control levels intoserial information containing a start bit, data, a parity bit, and astop bit. The receiver section of the UART 31 converts serialinformation, containing a start bit, data, a parity bit, and a stop bit,into a parallel data character. The UART 31 generates a parity bit forinformation transferred to the terminal unit device interface 22_(di),and it also checks the vertical parity of information received from thedevice interface terminal unit 22_(di).

The UART 31 has provisions for selecting various character lengths, oddor even parity generation/checking, and a choice of one or two stopbits. For use with a particular LCP, the UART 31 has options selected toprovide the following characteristics:

(a) a character containing seven data bits;

(b) generation/checking of even vertical parity;

(c) one stop bit.

The UART Multiplexor 27_(x) accepts an 8-bit character from either theAB (first two) digits of the terminal bus 47 or from the block checkcharacter register (BCCR) 33. The selected input is sent to the paralleldata input bus of the UART 31. The UART Multiplexor 27_(x) is used onlyfor the transfer of data or for a block check character from the LCPover to the terminal device interface 22_(di).

The block check character register (BCCR) 33 is a register whichconsists of eight separate flip-flops operated in the "toggle" mode,with inputs connected to the AB digits of the terminal bus 47. While theLCP is transferring data to the terminal device interface 22_(di), theBCCR 33 accumulates a block check character (BCC) to be sent to thedevice interface terminal unit 22_(di). When the LCP is receiving datafrom the device interface terminal unit 22_(di), the BCCR 33 alsoaccumulates a "block check character" to be checked against yet another"block check character" (BCC) sent from the device interface terminalunit 22_(di). The block check character accumulation is started upon thereceipt of the first character following a STX (start of text) or a SOH(start of heading) character, and continues until an ETX (end of text)character is received. Only messages and control sequences containing aSTX or a SOH character will cause a block check character (BCC) to beaccumulated.

The accumulation of the BCC consists of applying each character beingtransferred to the input of the BCCR 33 and performing a binary additionwithout carry (Exclusive OR function). Prior to each operation in whicha BCC will be accumulated in the BCCR 33, the register is cleared. Atthe end of a data transfer, the exclusive OR function is again performedbetween BCC's of the sending and receiving units. If no errors haveoccurred, both BCC's will be identical and the resultant value in theBCCR 33 will be "all zeros".

The block check character decoder 34 receives the output of the BCCR 33.At the end of a transmission from the peripheral terminal unit 50, a BCCis received and checked against the contents of the BCCR 33. IF the twoBCC's are identical, then the output of the BCCR is equal to "all zeros"and the decoder 34 generates the BCCOK level (Block check character OK)which is used in the BCC error logic.

The memory address register 36 is an eight bit register which developsaddresses for a 256 word LCP buffer 25₀₀. The register 36 is controlledso as to provide selective or sequential addressing of the buffer, asrequired by the data transfer operation which is to be performed.

The Termination Card 20_(0t) (of FIG. 2) provides a one-second timerwhich is enabled for operation only during a "read" operation when theLCP is conditioned to receive data from the peripheral unit, such as 50.When enabling inputs are active, the timer allows the peripheralterminal unit a one-second period in which to begin a transmission orcontinue an interrupted transmission over to the LCP. If the one-secondperiod elapses without a transmission from the peripheral terminal unit,a time-out flip-flop (TIMOUTF) is set, generating time-out level(TIMOUTL), and the LCP then initiates an end to the read operation bysetting an end flip-flop (ENDF). However, this timer can beprogrammatically inhibited from operating by placing the proper code inthe variant-1 digit of the Command Descriptor (FIG. 4B).

With reference to FIGS. 6B and 6D and the prior discussion regarding theData Flow section of the LCP, (Section B), the input multiplexor 24_(x1)provides the selection of a 17-bit word from three sources: the datainput lines B_(i), the output lines B₂₅ from RAM data buffer 25₀₀ or theperipheral device interface levels 24_(m) which are generated on theMaintenance Card (such as 20_(0m), FIG. 2) from the outputs ofpush-button switches on the maintenance panel. The selected levelsreceived by input multiplexor 24_(x1) are transferred to the OP coderegister 42 and variant register 43, the terminal bus multiplexor24_(x2) or the valid OP encoder 44, as required by the operation to beperformed.

The OP code register 42 receives the digital OP code of the CommandDescriptor C/D, and in conjunction with the output of the variantregister 43, specifies the operation to be performed by the LCP. Thevariant register 43 receives the variant digits contained in the CommandDescriptor C/D and, in conjunction with the output of the OP coderegister 42, specifies further details of the operation to be performedby the LCP.

The Valid OP Encoder 44 is a network which receives Command DescriptorC/D information at its input; then, if the OP code digits and thevariant digits 1,2, and 3 coincide with values representing validoperations for the LCP, this encoder develops the valid OP (VOP) level,which enables the Command Descriptor C/D to be loaded into the OP coderegister 42 and the variant register 43.

The LCP RAM buffer 25₀₀ is made of a network of 18 RAM devices, each oneof which has a capacity of 256 information bits. Reference to FIG. 6Cwill show more detail of the RAM buffer 25₀₀. The buffer network canstore 18-bits in each of its 256 address locations; 16 are data bits,one bit is a parity bit, and one bit is an end-flag bit (25_(e) of FIG.6C) to identify a word location containing an ending code.

Referring again to FIG. 6D, the terminal bus multiplexor network 24_(x2)provides selection of a 17-bit word from four sources: the inputmultiplexor 24_(x1) ; the UART 31 parallel data output line; the LPW24_(w) register output; and the Result Descriptor levels 24_(rd). Theoutput of the terminal bus multiplexor network 24_(x2) goes to theterminal bus 47. Appropriate voltage levels are provided to those LCPcomponents, (such as the data latch register 49, vertical paritygenerator/checker 48, buffer 25₀₀, LPW register 24_(w), decoder 52 andend code decoder 35 etc.) which have inputs received from the terminalbus 47.

The terminal bus 47 connects the output of the terminal bus multiplexornetwork 24_(x2) over to the following components: the data latchregister 49, the LCP RAM buffer 25₀₀, the LPW register 24_(w), thevertical parity generator/checker 48, the BCC register 33, the end codedecoders 52 and 35, and the UART multiplexor 27_(x).

The vertical parity generator/checker 48 generates odd parity for everyword transferred by the LCP over to the Main System 10. Thegenerator/checker 48 also checks for odd parity of every wordtransferred from the Main System over to the LCP. Each word to betransferred from the particular LCP over to the Main System 10 is firstplaced in the 17-bit register called the data latch register 49. Thedata latch register 49 then transfers the word over to the Main System10. The use of the data latch register increases the rate of datatransfer by allowing quicker access to data stored in the LCP RAM buffer25₀₀.

The longitudinal parity word (LPW) register 24_(w) is made of 16separate flip-flops operated in the "toggle" mode. It receives itsinputs from the terminal bus 47. When the Main System 10 sends a CommandDescriptor C/D, a Descriptor Link D/L, or data, over to the LCP, the LPWregister 24_(w) accumulates a LPW (longitudinal parity word) to bechecked against an LPW from the System 10. When the LCP sends data or aResult Descriptor R/D over to the System 10, the LPW register 24_(w)also accumulates an LPW to be sent to the System 10. Accumulation of theLPW consists of applying each word being sent or received to the inputof the LPW register 24_(w) and performing a binary addition withoutcarry (exclusive OR function).

The LPW register 24_(w) is initialized to "all ones" prior to eachoperation in which an LPW will be accumulated in the LPW register. Atthe end of a data transfer from the Main System 10, the exclusive ORfunction is performed between the accumulated LPW and an LPW from theSystem 10. If no errors have occurred, both LPW's will be identical andthe resultant value in the LPW register 24_(w) will be "all zeros".

In FIG. 6D the end code decoders 52 and 35 are used to determine thereceipt of an ending code character. Decoder 52 handles the AB digitsand decoder 35 handles the CD digits. The AB digit end-code decoder 52is used to identify an ending code in the first character position of aword from the Main System. This decoder is also used to identify anending code in any character sent from the terminal unit deviceinterface 22_(di). If decoder 52 receives such an ending code, it causesthe level EDCODE and the level SYSEND to be generated. The CD digitdecoder 35 is used to identify an ending code in the last characterposition of a word from the System. Receipt of such an ending code bydecoder 35 will cause the voltage level SYSEND to be generated.

The above mentioned elements of the Data Flow Section B has describeditems such as encoders, decoders, multiplexors, and parity generators.These elements are known in the state of the art and are described in1972 publications of the Texas Instrument Company entitled "TheIntegrated Circuits Catalog for Design Engineers" and "TTL - Data Bookfor Design Engineers". Further, the use of such multiplexors is shown inU.S. Pat. Nos. 3,408,632 and 3,972,030. The use of encoders and decodersis shown in U.S. Pat. Nos. 3,639,909, 3,673,576, 3,810,105, 3,972,023.

The Result Descriptor (R/D) which is latched in Data Latch Register 49for transmission to the Main System, is generated by the ResultDescriptor Levels logic 24_(rd) of FIG. 6D.

Result Descriptor Logic

The Result Descriptor logic is composed of flip-flop units such asdescribed in TTL Handbook for Design Engineers, published by TexasInstruments Company. This type of unit is called an Edge Triggered DualJ-K Flip-Flop and designated as V, Series 54H/74H.

As will be seen from FIG. 6D the Result Descriptor logic 24_(rd)receives signals from the valid OP encoder 44, the LPW encoder 51, theblock check character decoder 34 or vertical parity generator 48.

Thus should an invalid operations code occur, or a longitudinal orvertical parity word error occur, or a block check character erroroccur, then this is reflected in to the Result Descriptor logic 24_(rd)which generates a Result Descriptor word which reflects the conditionwhich occurred. This word can then be sent through the terminal busmultiplexor 24_(x2) and on through the terminal bus 47 into the DataLatch 49, after which at the appropriate time it can be passed on to theIOT and the system to notify the system of what was amiss in order thatcorrective action can be taken.

In summary, the Result Descriptor logic 24_(rd) generates ResultDescriptors to notify the Main System of unusual conditions which mightoccur. In this function the R/D logic is connected to receive signalsfrom:

(a) the vertical parity generator/checker 48;

(b) the Valid OP encoder 44;

(c) the LPW-register-encoder 51;

(d) the block check character register and decoder 33 and 34;

(e) the time-out clock signal;

(f) the conditional cancel signal.

The system address register 36_(s) and the device address register36_(d) are part of a counting logic device 36. These are used inconjunction with the 90 word memory buffer sections 25_(a) and 25_(b) ofFIG. 6C.

In a typical fashion the address registers 36_(s) and 36_(d) areoriginally set to "0". When the buffer memory area A (25_(a)) is beingfilled, the system address register 36_(s) counts from zero up to 89until the 90 spaces are filled up with the 90 words.

Meanwhile, the device address register 36_(d) could be emptying data(previously received) out of its memory buffer section B (25_(b)) andcounting the words (previously received) which have now been removed.Thus, there can be a simultaneous operation in which one buffer section,A, is receiving data and the other buffer memory section, B, isreleasing or removing data from its memory section.

In FIG. 6D the input multiplexor 24_(x1) selects, at any given moment ofcycle time, permits the passage of data from either the system or fromthe RAM buffer memory 25₀₀. (For test purposes signals can be insertedfrom the maintenance level logic 24_(m). This is done by a manualswitch.).

Selector logic 24_(s) is used to provide four output states which arefed to the input multiplexor 24_(x1). The input to the selector logic24_(s) is the SLAIN signal and the SLBIN signal. Table X-A shows howthese signals apply to Read and Write operations.

    TABLE X-A      CHARACTER BUFFER  INPUT TERMINAL BUS  ADRESS WRITE BIDIRECTIONAL     MULTIPLEXOR MULTIPLEXOR SELECT LEVEL ENABLE LEVELS LINE CONTROL SELECT     LEVELS SELECT LEVELS OPERATION EVNF ERWA ERWB IOSF SLBIN SLAIN SLBRAM     SLARAM SOURCE/DESTINATION OF DATA        X 1 1 0 0 0 0 0 ABCD DATA FROM SYSTEM TO          LCP BUFFER WRITE 0     0 0 0 0 1 0 0 AB DATA FROM LCP BUFFER TO          TERM. UNIT  1 0 0 0 1     0 0 0 CD DATA FROM LCP BUFFER TO          TERM. UNIT  0 1 0 0 X X 0 1 AB     DATA FROM TERM. UNIT TO          LCP BUFFER READ 1 0 1 0 X X 0 1 CD DATA     FROM TERM. UNIT TO          LCP BUFFER  X 0 0 1 0 1 0 0 ABCD DATA FROM     LCP BUFFER          TO SYSTEM

Thus, the selector logic 24_(s) may be made to signal the following fourstates:

a "first" state to signify "data" from the Main System 10;

a "second" state to signify RAM buffer character AB of a RAM word;

a "third" state to signify the RAM character CD of the RAM word;

a "fourth" state to signify "maintenance interface logic".

The terminal bus multiplexor 24_(x2) of FIG. 6D (which corresponds toMUX2 of FIG. 6B) serves the function of transferring, at any given cycletime, data from the UART 31, a Result Descriptor R/D from RD logic24_(rd) or signals from the input multiplexor 24_(x1), over to theterminal bus 47 which can transfer data into the RAM buffer memory 25₀₀or to the UART multiplexor 27_(x). This last named multiplexorcorresponds to MUX3 of FIG. 6B and provides the function of, at anygiven cycle time, transmitting data or a block check character on to theUART 31 for transmission to the peripheral unit 50.

The Status Count Register 53 (STC) is a four-bit register. This registerdevelops Status Count levels (STCnL) for use in the LCP and levelsdesignated LCSTUn (LCP Status Levels) for transmission to the MainSystem 10. In conjunction with providing floating logic levels, the STCregister 53 also controls the sequencing of operations for the LCP. EachStatus Count developed by the STC register 53 specifies a differentphase of operation in the execution of a Command Descriptor C/D, as waspreviously outlined in connection with FIG. 6A. The decoder 54 is abinary coded decimal (BCD) to decimal decoder which changes the BCDvalues of the STC register 53 to decimal values required by the LCPsystem.

In FIG. 6D, the Status Count Register 53 and decoder 54 is a standardfour bit binary counter and is described in the TTL Handbook for DesignEngineers published by Texas Instruments Company, Inc. 1962, anddesignated as a "Synchronous four-bit Counter".

Thus, this counter is enabled to count up or down and also can bepreloaded to a set value as a normal condition. Signals supplied to theStatus Counter register 53 are logically handled in order to provide a"Status Count" in the register 53 which will reflect the conditions ofthe Line Control Processor over to the IOT 10_(t) of the Main System sothat the Main System can then logically determine the next action totake.

The Status Count register 53 (STC) uses inputs from various encodingdevices. This four-bit register develops Status Count levels for use inthe Line Control Processor and the LCSTU levels (signalling the StatusCount of a selected LCP, see FIG. 6E) for transmission to the MainSystem. In conjunction with providing floating logic levels, the STCregister controls the sequencing of operations for the Line ControlProcessor (LCP). Each Status Count developed by the STC registerspecifies a different phase of operation in the execution of a CommandDescriptor (C/D) by the Line Control Processor.

The STC decoder 54 of FIG. 6D is a BCD-to-decimal decoder which changesthe binary coded decimal values of the STC register 53 into decimalvalues required by the Line Control Processor.

In FIG. 6D, the STC register 53 is seen receiving its input signals fromFlow Control Logic 53_(f) and Processor Logic 53_(p). These logic unitsare standard type logical circuitry well known in the art. The ProcessorLogic 53_(p) provides for the switching of bistable devices for enablingexecution of OP codes or instructions given to the LCP by the MainSystem 10.

In FIG. 6B, switching of the first multiplexor 24_(x1) is controlled bySelector 24_(s) having input lines SLAIN, SLBIN hereinafter described atpage 188. Multiplexors 24_(x2) and 27_(x) are switched by controls24_(2c) and 24_(3c) which connect to Processor Logic 53_(p).

Hardware wise this type circuit is described in the book TTL Handbookfor Design Engineers, published by Texas Instruments Company, 1962. TheStatus Count register is a counter and register which operates as anUp-Down Counter and one typical type is designated as a synchronous4-bit counter, SN 74161. The decoder portion is designated a four-tenLine Decoder also described in the book TTL Handbook for DesignEngineers, published by Texas Instruments Company, and identified as SN7442A.

Reference to FIG. 6E will be instructive in reviewing the systeminterrelationships between the major LCP elements involved in regard tothe logic and control signals operating between these elements. FIG. 6Eshows the major logic and control lines between the IOT (Input-OutputTranslator) 10_(t), the Distribution Card 20_(0d) (for the Base Module20₀), the particular Line Control Processor LCP 20₀₀ and the peripheralterminal unit 50.

First referring to the lowermost group of control lines, the LCP 20₀₀and its Distribution Card 20_(0d), the designation LCPREQ (n) is a groupof eight "request" lines where the letter "n" represents the numbers 0-7for each specific LCP in the Base Module 20₀. Each of these signals isdriven by one particular LCP over to the Distribution Card 20_(0d). Thissignal is used by a particular LCP to "request" a connection to theSystem 10 and causes the Distribution Card 20_(0d) to set up a "PollRequest".

The next designation LCPCON is the designation for "LCP connected". Thisline is driven by the connected LCP (0-7) to the Distribution Card20_(0d). This signal is driven by the LCP when it detects its ownparticular LCP address and it is not in an "off-line" condition. Thesignal is a response to the LCP address and signifies to theDistribution Card 20_(0d) the presence of the LCP addressed.

The designation LCPSTL signifies "LCP Strobe Level". This line is drivenby the "connected" LCP over to the Distribution Card. It is theparticular LCP's designation of "send" or "acknowledge", depending onthe data direction involved.

The IOSND designates I/O send. This line is driven by the "connected"LCP to the Distribution Card 20_(0d). This line defines the direction ofthe bidirectional data lines marked DATA (xn). When this line is activelow, the data lines will be driven by the Distribution Card 20_(0d) tothe Main System 10 via IOT 10_(t).

The LCSTU (n) designates the status of the particular LCP where "n" maydesignate either of LCP's 0-7. This line is driven by theparticularly-connected LCP to the Distribution Card 20_(0d) and revealsthe "Status" of the LCP as shown in FIG. 6A.

Referring to FIG. 6E, a number of connections are provided as betweenthe LCP, such as 20₀₀ and the Distribution Card 20_(0d). The DATA (xn)represents the "message level interface" (as previously shown in FIG. 5Eof which the lower 16 lines are the data lines for the digits ABCD). Thenext higher line is the PARITY line which carries the parity bits. These17 lines constitute the message level interface and are of abidirectional nature, that is to say, transmission may occur in eitherdirection along these lines depending on the logic control lines used todetermine the direction of transmission.

The designation EMRREQ in FIG. 6E signifies the "emergency request"line. This line is driven by one or more LCPs to the Distribution Cards.The LCP may drive the emergency request line at any time. The emergencyrequest signifies that an LCP needs system access quickly to avoid adata transfer failure. Only LCP's whose lack of system access willnecessitate operator intervention or difficult error recovery, willdrive the emergency request in conjunction with their LCP request. ThoseLCPs which are not emergency requesting, will disable their LCP requestwith this line. A Distribution Card detecting an emergency request, willcause a Global Priority of "seven" to be transmitted to the Main System10 during a "Poll Request".

The designation TERM in FIG. 6E designates a "terminate" voltage level.This is generated on a Distribution Card and is sent to the LCP toterminate or end an operation.

The designation LCPAD "n" in FIG. 6E designates the LCP address (where"n" can be 0-7) to designate the individual LCPs. One of these eightsignal lines is driven by the Distribution Card to each particular LCP.The receiver in the LCP will be jumpered to the proper line. This signalis functionally a connection line to the LCP. An LCP receiving its LCPaddress is "connected" to the Main System 10 through the DistributionCard.

The STIOL in FIG. 6E signifies the "Strobe I/O Level". This line isdriven by the connected Distribution Card. It represents the System's"send" or "acknowledge" depending on the data direction.

The ARQOUT line of FIG. 6E is the output end of the Distribution Cardwhich has an input designated ARQIN. These represent "access request in"and "access request out". These signals are driven and received byDistribution Cards only and consist of short lines between adjacentDistribution Cards. They are used during "Poll Test" to resolveDistribution Card priority. The lines DCB 1 and the DCB 2 representDistribution Card "busy" levels. These are generated on each activeDistribution Card in a Base Module to resolve Distribution Card priorityin the module during a "Poll Request" sequence.

The PTALB line designates "Poll Test Active Level". This is abidirectional signal level between Distribution Cards in the same BaseModule. A Distribution Card performing a "Poll Test" operation sendsthis level to the other Distribution Cards, thus inhibiting them fromconducting a "Poll Test" or a "Poll Request" sequence.

Each Base Module may service not only one "main system" 10 via itsDistribution Card (20_(0d), FIG. 2) but may be provided with multipleDistribution Cards to cooperate with and service other host "mainsystems". Each Distribution Card in a Base Module can service adifferent host system and each host system would follow the same basicorganization shown in FIG. 3.

The REQACC line designates "Request Access". This line is driven by andreceived by Distribution Cards only. The line is used to signify aninterrupt request as being "active" by the Distribution Cards.

The BUSY line of FIG. 6E designates a Base Module "Busy" level. This isa bidirectional signal level developed on a Distribution Card when thatcard has made a "connection" with the Main System 10. The level is sentto other Distribution Cards on the same Base Module to indicate that theLCP backplane is in use.

Now, further in reference to FIG. 6E, the relationships between the IOT10_(t) and the Distribution Card 20_(0d) will be discussed. At the upperleft of FIG. 6E, the LCPST designates the LCP Strobe Pulse. This isgenerated on a Distribution Card from the LCP strobe level and is senton to the Main System via the IOT 10_(t).

The PB/ST 2 designates "Port Busy" or the LCP status 2 line. This lineresides on the message level interface as shown in FIG. 5E. In the"unconnected" state, this line indicates a Port Busy condition during a"Poll Test" algorithm. In the "connected state", this line carries bit 2of the LCP's status to the System 10.

The IP/ST 4 designates an Interrupt Request or a Poll Test parity error,or an LCP status 4 line. In the unconnected state, this line is used tocarry an "Interrupt Request" from the LCP or else to indicate an addressparity error during a "poll test" connection attempt. An InterruptRequest indicates that a LCP is requesting access to memory. In the"connected" state, this line carries bit 4 of the LCP's status to theMain System.

The ER/ST 8 designates "emergency request" or the LCP status 8 line. Inthe "unconnected" state, this line represents an emergency request fromthe LCP. "Emergency request" designates that a LCP needs immediateaccess to the Main System. In the "connected" state, this line carriesbit 8 of the LCP's status to the Main System. Once connected, the LCPindicates its System Memory requirements by its status. The LCP statusis gated continuously and may only be considered valid by the System atLCP "Send/Acknowledge" time.

Further in FIG. 6E to the connections between the IOT 10_(t) and theDistribution Card 20_(0d), the connections designated PARITY and DATA"xn" refer to the message level interface lines previously discussed.The CS/ST 1 designates "Channel Select" or LCP status 1 line. In the"unconnected" state, these lines carry "Channel Select" from the System10 to the Distribution Card. "Channel Select" is used in conjunctionwith "address select" in both connection algorithms. However, in the"connected" state, this line carries bit 1 of the LCP's status to theMain System 10. This line is a bidirectional line. The receiver on theDistribution Card will be any standard TTL device. The driver on theDistribution Card will be a tri-state driver such as a 8097/8098(National Semiconductor Corp.) or equivalent which will be active onlyin the connected state.

The TRM designates the "terminate" level. This is sent from the MainSystem 10 to a Distribution Card when a data transfer operation is to beterminated.

The ADDSEL line of FIG. 6E designates "address select". This signal lineindicates that the Main System is connected or is attempting connectionto a specific LCP. This line is used in conjunction with "ChannelSelect" for both connection algorithms to achieve connection. Once aconnection to the LCP is achieved, the System and LCP remain connecteduntil the signal line is inactivated by the System. When the line isactive, the System can be considered "busy".

Again referring to FIG. 6E, the AG/SIO designates "access granted" or"Strobe I/O". When the interface is in an "unconnected state", this linecarries an "access granted" signal. "Access granted" is used toacknowledge an Interrupt Request for connection and to begin a "PollRequest" algorithm. With the interface in a "connected" state, this linecarries a "Strobe I/O" signal. This signal is the System'sSend/Acknowledge line in transferring information between the System 10and the LCP Base Module. The actual signal is a 100 nanosecond minimumpulse sent from the System and latched by the Distribution Card. TheDistribution Card will generally clip the first 50 nanoseconds from thesignal to allow for cable settling time.

In regard to FIG. 6E, the control signals as between the LCP 20₀₀ andthe peripheral terminal unit 50 indicate a line designated RMDTLN. Thisdesignates Remote Data Line Level. This is a bidirectional signal levelwhich permits the transfer of serial data between the LCP and theperipheral terminal unit in one direction or the other direction asdetermined by the level.

Discussed here and below are the operational sequences of the LCP. Thelogic terms are referred to as either being active or inactive in orderto avoid any ambiguity that might result from using the terms True andFalse.

Receipt of Instructions by Line Control Processor

Previously in FIG. 6A, the logic flow involving the Status Counts (STC)between the LCP 20₀₀ and the Main System 10 was discussed. Now referringto FIG. 7A there will be seen in greater detail a simplified flowdiagram illustrating the receipt of instructions by the LCP. This flowchart shows the basic actions of the LCP during receipt of instructionsand also shows those actions which can occur due to modification of theoriginal instructions, the receipt of a time-out level, and theoccurrence of error conditions.

Prior to receiving any of the seven possible instructions from the MainSystem 10, the LCP is normally in an "idle" state at Status Count 3.However, the LCP can also be in a STC 3 during a "Read" operation,awaiting either a conditional cancel instruction from the Main System10, or a data transmission from the peripheral terminal unit, such as

The following will describe the actions of the LCP during receipt ofinstructions from the System 10 and during preparation for theinstruction execution. These actions are itemized as (a), (b), and (c).

(a) System-LCP connection: with the LCP in STC 3, the System makes aconnection with the LCP through a "Poll Test" sequence, and the LCPreceives its unique address level (LCPAD) (n), as was illustrated inFIG. 6E. The receipt of LCPAD (n) causes the LCP to send the LCPconnection level (LCPCON, FIG. 6E) to the associated Distribution Card20_(0d) and generates LCPADL (LCP Address Level), which "enables"portions of the LCP system logic section. The address level LCPAD (n)also enables the LCP backplane network by generating a gate system level(GATSYS). Then a strobe (STIOL) is received from the Distribution Card(20_(0d), FIG. 6E) causing STIOF (Synchronous Strobe Flip-Flop) to beset. The setting of STIOF activates the desired module of the LCP bysetting RECVF (Receive Flip-Flop), enables setting of the LPW register(24_(w), FIG. 6D) to logic "1's", and sets selected flip-flops to abeginning state. The Command Descriptor C/D is received in the LCP andis loaded into the OP code register 42 and variant registers 43 (FIG.6D). Receipt of the C/D results in an LPW being placed into the LPWregister 24_(w). The C/D is checked for validity and the valid OPflip-flop (VOPF) is set. The LCP then steps from STC 3 over to STC 11(FIG. 7A) to receive an LPW from the System 10.

(b) Receipt of LPW by the LCP: In FIG. 7A at STC 11, a longitudinalparity word (LPW) is received from the System 10 and is checked againstthe contents of the LPW register 24_(w) to validate longitudinal parityof the C/D transfer. Vertical parity is also checked, then a verticallevel OK (VLOK) and vertical parity OK level (VPAROK) is set. The LCPbuffer address is preset to 253 in the memory address register MADR 36(FIG. 6D), and setting of the LPW register 24_(w) to logic "1's" isagain enabled; then the LCP steps to STC 6 to receive the DescriptorLink D/L from the System 10.

(c) Receipt of Descriptor Link and Descriptor Link LPW: at STC 6, theLCP receives the two words of the Descriptor Link D/L from the System 10and a LPW is accumulated in the LPW register 24_(w). A LPW is thenreceived from the System 10 and is checked against the contents of theLPW register 24_(w). The Descriptor Link D/L and the LPW are stored inbuffer address locations specified by the memory address register MADR36 as addresses 253, 254 and 255 (FIG. 6C). From STC 6, the LCP branchesto STC 8 for a "Write" operation, or to STC 1 for a "Read" operation, orto STC 7 if a Descriptor Link error occurred.

There are alternate flow path situations such as: (a) when a"conditional cancel" instruction is received from the System 10, or (b)a data transmission is received from the peripheral terminal unit, suchas 50, or (c) a time-out level is generated, or (d) a receipt of testinstructions. To further amplify these alternate flow path situationsper FIG. 7A: (a) receipt of Conditional Cancel Instruction: at STC 3, ifa conditional cancel instruction is received from the System 10, whilethe LCP is awaiting a transmission from the peripheral terminal unit 50,a cancel flip-flop (CANCF) is set and the LCP steps to STC 11 to receivea Command Descriptor longitudinal parity word, LPW. From STC 11, the LCPsteps to STC 7 and sends a Result Descriptor to the System 10,indicating that the cancel operation is completed.

(b) Receipt of Transmission from the Peripheral Terminal Unit: at STC 3during a "Read" operation, if the terminal busy flip-flop (TRMBSYF) isset, indicating that terminal unit has started transmitting, the LCPsteps to STC 1 to receive data from the peripheral terminal unit. TheLCP continues to receive data and completes the remainder of the Readoperation in accordance with instructions contained in the CommandDescriptor C/D.

(c) Receipt of Time-Out Level: during a "Read" operation, with the LCPin STC 3 awaiting a transmission from the peripheral terminal unit (andif the 1-second timer is not inhibited) then if there is a 1-seconddelay in receiving the transmission, the time-out level (TIMOUTL) isgenerated. With TIMOUTL active, the end flip-flop (ENDF) is set, theterminal complete (TMCNP) level is generated, and the LCP steps toSTC 1. At STC 1 a request for reconnection to the System is initiatedand the LCP steps to STC 5, FIG. 7B. At STC 5 with ENDF set, the Readoperation is terminated and the LCP steps to STC 7 to send a ResultDescriptor, R/D, to the System 10. A time-out level can also be receivedwith the LCP at STC 1.

(d) Receipt of Test Instructions: at STC 11, FIG. 7A, if TESTF (TestFlip-Flop) is set indicating that a test instruction was received, theLCP completes the test operation by stepping to STC 7 and sending aResult Descriptor R/D to the System 10.

Error Conditions: the occurrence of two types of error conditions (ea)and (eb) during the receipt of instructions will be acted upon by theLCP, as follows: (ea) Command Descriptor parity error: In FIG. 7A, atSTC 11, if the VLOK (Validity Level OK) level is not active, or if VOPF(Valid Operation Flip-Flop) is not set, the LCP steps to STC 7 to send aResult Descriptor R/D containing a descriptor error to the System; (eb)Descriptor Link parity error: at STC 6, if the VLOK level is not active,the LCP steps to STC 7 to send a Result Descriptor R/D containing aDescriptor Link error to the System 10.

Write Operation

Referring to FIG. 7B, there is seen a sequential logic diagram which issimplified to show the steps involved in the "Write" operation. Let usassume that one buffer load of data will be transferred from the System10 to the peripheral terminal unit 50, followed by a partial buffer ofdata containing an ending code character in the last character position(CD digits) of a word.

The following steps (a through i) describe actions of the LCP, such as20₀₀, during transfer of data from the System 10 over to the LCP, andfrom the LCP to the peripheral terminal unit, such as 50.

(a) Receipt of data from system: at STC 6, if a "Write" operation isspecified by the Command Descriptor C/D, the LCP enables the setting ofthe LPW register 24_(w) to logic "1's", then steps to STC 8 to receivedata from the System 10. An IOSF (I/O Send Flip-Flop) is used and put ina reset state at this time to enable the bidirectional data lines fortransfer of data from the System 10 over to the LCP. There are providedmultiplexor control levels SLAIN (Select A Input Multiplexor) and SLBIN(Select B Input Multiplexor). These are both inactive, connecting thedata lines to the input multiplexor network 24_(x1) of FIGS. 6B and 6D.There are other multiplexor control levels SLARAM (Select A LevelTerminal Bus Multiplexor) and SLBRAM (Terminal Bus Multiplexor Select BLevel). These also are both inactive, connecting the input multiplexornetwork 24_(x1) to the input of the Terminal Bus Multiplexor Network24_(x2).

At STC 8, the Receive Flip-Flop (RECVF) is set, activating the writemodule of the LCP. The setting of RECVF causes the write enable level(WESYS) for the LCP buffer to be active. Thus, data is transferred fromsystem Main Memory 10_(m) over to the LCP buffer 25₀₀, one word at atime, by way of the terminal bus 47 of the LCP. An Asynchronous Strobe(STIOL) from the associated Distribution Card 20_(0d) (FIG. 6E)accompanies the transfer of each word, and as each word is received bythe LCP, the LCP sends a strobe level (LCPSTL) to the System 10 to"acknowledge" receipt of the word. As each word is placed on theterminal bus 47, then, in addition to being sent to the buffer 25₀₀, itis also applied to the input of the vertical parity generator/checker48, the LPW register 24_(w) and the end code decoders 52 and 35.Vertical parity is checked and a longitudinal parity word is accumulatedin the LPW register 24_(w). Transfer of words continues until the nextto last data word address 251 is attained in the Memory Address Register36. The LCP then steps to STC 10 of FIG. 7B to receive one final wordfrom the System. At STC 10, the LCP receives the final word to fill thebuffer, and then steps to STC 12 to receive an LPW from the System 10.

(b) Receipt of LPW and disconnect from the System 10: at STC 12, the LCPreceives an LPW from the System 10 and checks it against the LPWaccumulated in the LPW register 24_(w) during the data transfer. The LCPthen enables setting of the LPW register 24_(w) to logic "1's" and stepsto its STC 1, disconnecting from the System 10 in order to transfer datato the peripheral terminal unit, such as 50. Terminal bus multiplexercontrol levels SLARAM and SLBRAM (Select A and Select B of 24_(x2)) areboth inactive thus to connect the output of the buffer 25₀₀ with theinput to the terminal bus multiplexor network 24_(x2). The inputmultiplexor 24_(x2) has control levels SLAIN (Input Multiplexor Select ALevel) and SLBIN (Input Multiplexor Select B Level) which will becontrolled during the data transfer by the state of the even flip-flop(EVNF) in order to access a character alternately from the AB digits andthe CD digits of a word in the buffer 25₀₀.

(c) Transfer of Data to Peripheral Terminal Unit: with further referenceto FIG. 7B, at STC 1, the receive flip-flop (RECVF) is reset, thusenabling the receive module of the LCP. The terminal start level (TERST)is generated to prepare the LCP for operation with the peripheralterminal unit. The TERST level enables the setting of master clear UARTflip-flop (MCUARTF) in order to clear the UART 31 (FIG. 6D). The settingof a terminal active flip-flop (TRMACTF), a send flip-flop (SENDF), andthe terminal busy flip-flop (TRMBSYF) are also enabled, activatingterminal control logic for a Write operation and specifying that theperipheral terminal unit is in a "busy" state. The Memory AddressRegister 36 (FIG. 6D) is set to MADR O to access the first word in thebuffer 35₀₀. In the UART 31, the "transmitter holding register empty"(THRE) level is active, and the setting of the UART empty flip-flop(UARTETF) is enabled to provide a strobe level to the UART multiplexor27_(x).

The UART 31 accepts one character at a time from the LCP buffer 25₀₀.The even flip-flop (EVNF) is used in conjunction with the Memory AddressRegister 36 to control accessing of characters. When loaded with acharacter, the UART 31 transfers the character serially over to theperipheral terminal unit, such as 50. As each character from the buffer25₀₀ is placed on the terminal bus 47, it is also applied to the inputof the block check character register (BCCR) 33, which (after a STX/SOH,"start of test/start of heading" character has been received) begins toaccumulate a block check character during the data transfer. The UART 31continues to accept characters from the buffer 25₀₀, then transferringthem to the peripheral terminal unit 50, until memory address level MADR252 is attained in the Memory Address Register 36, indicating that thelast word in the buffer has been accessed.

(d) Request for Reconnection to System 10: the memory address level MADR252 causes the buffer transfer flip-flop (BFXFRF) to be set, indicatingthat the buffer 25₀₀ needs service, and the LCP initiates a request forreconnection to the System by enabling the setting of the LCP requestflip-flop LCPRQF. The setting of IOSF (I/O Send Flip-flop whichindicates the direction of data flow on the message level interface) isenabled to condition the data lines for transfer of data to the System10, and the setting of MADR 253 level is enabled to allow access to theDescriptor Link D/L (FIG. 6C). The LCP then steps to STC 5 of FIG. 7B tosend the Descriptor Link D/L to the System 10. There are floating logiclevels which generate LCPADL (LCP Address Level) when the LCP addresslevels (0-7), LCPADn, is received from the associated Distribution Cardduring the reconnection sequence, and the LCP generates a level calledgate system (GATSYS) to enable the backplane network. The level LCPconnected (LCPCON) is sent to the Distribution Card 20_(od) to indicatethat the LCP is connected.

(e) Transfer of Descriptor Link and the Descriptor Link LPW: in FIG. 7B,at STC 5, the transmit flip-flop (XMITF) is set, activating the "Read"module of the LCP. The LCP transfers the Descriptor Link D/L and the LPW(previously received at STC 6) back to the System 10. The LCP enablesthe setting of the LPW register 24_(w) to logic "1's" and if the MainSystem has more data to send, the LCP steps again to STC 8 to receiveadditional data from the System 10.

(f) Receipt of Additional Data and Ending Code from System 10: at STC 8,the actions of the LCP while receiving the "second" buffer load of datafrom the System 10 are the same as those performed during receipt of thefirst buffer load, up to the point that an "ending code" is recognizedby the terminal bus 47. When an "ending code" in the last characterposition (CD digits) of a word is placed on the terminal bus 47, then asystem end level (SYSEND) is generated. SYSEND level causes the datainput for the end-flag 25_(e) of FIG. 6C (RAM 18 L) to be active and theend-flat bit (ENDFG) and the ending code character are both stored inthe current buffer address. The LCP then steps to STC 12 to receive anLPW from the System 10.

(g) Receipt of LPW and Disconnect from System 10: at STC 12 of FIG. 7B,the LCP receives the longitudinal parity word LPW and checks it againstthe LPW accumulated in the LPW register 24_(w). The LCP then steps toSTC 1, disconnecting from the System 10, to transfer the remaining dataand the ending code to the peripheral terminal unit.

(h) Transfer of Data and Ending Code to Peripheral Terminal Unit: at STC1, the actions in transferring the remaining data to the peripheralterminal unit are the same as those performed during transfer of thefirst buffer load, up to the point that an "ending code" is recognizedon the terminal bus 47. When an ending code is placed on a terminal bus47 from the output of the buffer 25₀₀, the ending code is transferredand the end flip-flop (ENDF) is set. The accumulated block checkcharacter in the BCCR 33 (if a BCC is being generated) is thentransferred to the peripheral terminal unit such as 50. SENDF (sendflip-flop) and TRECF (terminal receive flip-flop) are both in a resetstate, causing terminal complete (TMCMP) level to be active. Theterminal complete level causes the LCP to initiate a request forconnection to the System 10.

(i) Request for Reconnection to Terminate Write Operation: the LCPrequests a reconnection to the System by enabling the setting of LCPRQF(LCP Request Flip-flop). In conjunction with the reconnection, the LCPsteps to STC 5 of FIG. 7B, sends the Descriptor Link D/L to the System10 and then steps to STC 7 to send a Result Descriptor R/D to the System10.

The above discussion completes the explanation of the general flow pathfor a "Write" operation in which more than one buffer load of data wastransferred, and in which the operation was concluded by receipt of an"ending code". This describes the normal situation. However, there couldbe alternate flow paths and possible error conditions which might occuras follows, in reference to FIG. 7B. The following items (a) through (c)describe the actions of the LCP when "modifications" to the originalWrite instructions are made by the System 10 or the LCP.

(a) Request for Emergency Access to System 10: during transfer of datafrom the LCP to the peripheral terminal unit 50, when the LCP buffer25₀₀ is completely empty, a flip-flop BFXFRF is set. This is the buffertransfer flip-flop which is located on the Terminal Card; this flip-flopis set when the LCP buffer is filled with data from the terminal unit,or when emptied of data during transfer of data from the LCP to theperipheral terminal unit. When BFXFRF is set, this enables the settingof LCPRQF (LCP Request Flip-flop, which, when set, indicates that theLCP requires access to the Main System Memory 10_(m)). The setting ofthe LCPRQF initiates a request for reconnection to the System 10 toeither send data to the Main System or to obtain more data if the bufferis empty. If a reconnection is not completed prior to the time thetransmitter-holding register of the UART 31 is ready to accept anothercharacter, the LCP causes the emergency request level (EMRREQ) to begenerated. The EMRREQ level is sent to the associated Distribution Card20_(od) to initiate an emergency request for reconnection to the system.

(b) Receipt of Ending Code (AB digits): if an ending code is identifiedin the first character position (AB digits) of a word from the System10, then EDCODE (end code level) is generated. EDCODE is generated onthe terminal control card when an end code character is in the A and Bdigits of the terminal bus 47. Also generated is SYSEND (System End CodeLevel). When active, the SYSEND level indicates that an end codecharacter is on the terminal bus 47. At STC 8, the ENCODE level enablesthe setting of a character end flip-flop (CHARENF), and the SYSEND levelgenerates the 18th bit end-flag, RAM 18 L. The Write end-flag level isgenerated on the terminal control card from the EDCODE level; this isthe data input level for the end-flag RAM of the LCP buffer 25₀₀. Theending code and the ENDFG (end-flag level is generated on the data flowcard from RAM 18 L; when active, this level identifies the address of anend code in the LCP buffer) are stored in the current buffer address ofthe LCP, and the LCP steps over to STC 12 (FIG. 7B) to receive alongitudinal parity word LPW. At STC 12, the LCP receives an LPW fromthe System 10 and checks it against the accumulated LPW in the LPWregister 24_(w). The LCP then steps to STC 9 to initiate decrementing ofthe System Memory Address. (The address must be decremented by twodigits to accurately reflect the address of the ending code in SystemMemory). From STC 9, the LCP steps over to STC 1 to transfer data andthe ending code to the peripheral terminal unit 50. At STC 1,recognition of the ending code on the terminal bus 47 causes the LCP toperform the same actions described during the previous "Write" operationat STC 1 when data, ending code, and block check characters aretransferred to the peripheral terminal unit 50, after which the LCPdisconnects from terminal unit 50 and reconnects to the System 10 andterminates the "Write" operation.

(c) Receipt of Terminate Signal from System 10: a terminate signal (TERMlevel, FIGS. 6C, 6E) is sent from the System 10 to the LCP wheneverSystem Memory space designated for LCP operation is to be exceeded.During a "Write" operation, the TERM level can be received at STC 8, STC10, or STC 12, FIG. 7B. The actions of the LCP upon receipt of the TERMlevel (Terminate Level) depend upon the Status Count in which the LCP isoperating, and upon whether or not the receipt of TERM level is precededby a receipt of an "ending code" from the System as follows:

(1) Receipt of Terminate Signal Before Ending Code: if the TERM level isreceived at STC 8 or STC 10, the LCP steps over to STC 14. At STC 14,regardless of whether TERM level remains active or is now inactive, theLCP steps over to STC 12, receives and checks a longitudinal parity wordLPW, then steps over to STC 7 to send a Result Descriptor R/D to theSystem 10. If an ending code is received in the CD digits (lastcharacter) of a word at STC 8 or STC 10, and the TERM level is alsoreceived, the LCP steps to STC 14. At the STC 14, if the TERM level isstill active, the ending code was not placed in the LCP buffer 25₀₀. TheLCP then steps to STC 12, receives and checks an LPW, then steps over toSTC 7 to send a Result Descriptor R/D to the System 10.

(2) Receipt of Terminate Signal After Ending Code: if an ending code isreceived in the CD digits of a word at STC 8 or STC 10, the LCP steps toSTC 12 to receive LPW. At STC 12, if the TERM level is now received, theending code is transferred to the LCP buffer 25₀₀ and the LCP steps overto STC 1 to transfer remaining data and the ending code to theperipheral terminal unit 50. At STC 1, recognition of the ending code onthe terminal bus 47 causes ENDF to be set. (End flip flop: when set,this flip-flop indicates that the terminal control section of the LCPhas ended its operation). The setting of ENDF indicates that there is nomore data to be transferred; after the data, ending code, and blockcheck character are transferred to the peripheral terminal unit 50, theLCP disconnects from terminal 50, reconnects to the System 10, toterminate the "Write" operation.

As illustrated hereinunder, at STC 1, the recognition of the ending codeon the terminal bus 47 causes the ENDF (end flip-flop) to be set. Thesetting of ENDF indicates that there is no more data to be transferred;after the data, ending code and block check character are transferred tothe peripheral terminal unit 50, the LCP reconnects to the System 10 toterminate the "Write" operation.

If an ending code is received in the AB digits of a word at STC 8 or STC10, and the TERM level is also received, the LCP steps to STC 14. At STC14, if TERM level is inactive, the whole word containing the ending codein the AB digit was transferred to the LCP buffer 25₀₀. A correction ofSystem Memory Address is necessary. The LCP steps to STC 12, receivesand checks the LPW, then steps to STC 9 to initiate decrementing of theSystem Memory Address. The LCP then steps to STC 1 to transfer data andending code to the peripheral terminal unit 50.

If the TERM level was still active at STC 14, then only the ending codecharacter was transferred to the LCP buffer 25₀₀ and no correction ofSystem Memory Address is required. The LCP steps to STC 12, receives andchecks the LPW, then steps directly to STC 1 to transfer data and theending code over to the peripheral terminal unit 50.

Error Conditions: During a "Write" operation the following errorconditions (a,b,c,d) will be acted upon by the LCP:

(a) Access Error: after transmitting EMRREQ level to the associatedDistribution Card, if the LCP does not receive a reconnection to theSystem 10 prior to the time the UART 31 is completely empty, the LCPenables the setting of the access error flip-flop (ACCERF). The settingof ACCERF enables setting of the end flip-flop (ENDF), and the LCPinitiates a request for reconnection to the System 10 to terminate the"Write" operation and to send an error Result Descriptor R/D to theSystem 10.

(b) System Vertical Parity Error: during transfer of data from theSystem 10 to the LCP, if the vertical parity is not O.K. and the VPAROKis not active after each check of vertical parity, then the verticalparity error flip-flop (VPERF) is set to indicate the existence of avertical parity error. The absence of VPAROK level also prevents thevertical longitudinal OK level (VLOK) from being generated, and at STC12, the LCP steps over to STC 7 to send an error Result Descriptor R/Dto the System 10.

(c) Longitudinal Parity Error (FIG. 7B): when the longitudinal parityword is checked after a data transfer from the System 10 to the LCP, iflongitudinal parity OK level (LPOK) is not active, the longitudinalparity error flip-flop (LPERF) is set to indicate existence of alongitudinal parity error. The absence of LPWOK level (the LPW OK level:is generated on the data flow card from the terminal bus 47 levels; whenactive, it indicates to the System Logic Section of the LCP that the LPWis correct) prevents VLOK level from being generated, and at STC 12, theLCP steps over to STC 7 to send an error Result Descriptor R/D to theSystem 10.

(d) Terminal Vertical Parity Error: during transfer of data from the LCPbuffer 25₀₀ to the UART 31, if the vertical parity OK (VPAROK) leveldoes not remain active for each character transferred, the terminalvertical parity error flip-flop (TVPERF) is set to indicate existence ofa vertical parity error. When the LCP reconnects to the System 10 andterminates the "Write" operation, the Result Descriptor R/D sent to theSystem 10 at STC 7 will indicate the parity error.

Read Operation:

Referring to FIG. 7C, there is seen a simplified logic chart showing the"Read" operation. A "Read" operation is generally accomplished inconjunction with some form of "Write" operation. As an example, assumingthat a "Write" operation has been completed and the peripheral terminalunit 50 has responded with an acknowledge character (ACK), indicatingthat the peripheral terminal unit 50 is now capable of sendinginformation. Again, assuming there will be no delay in receipt of datafrom the peripheral terminal unit 50, and that one buffer load of datawill be received followed by a partial buffer of data containing anending code. It is also assumed that the ending code will be received insuch a way that it will be placed in the last character position (CDdigits) of a word in the LCP buffer 25₀₀ (FIG. 6C).

General Flow Path: The following paragraphs (a) through (l) describe theactions of the LCP during transfer of data from the peripheral terminalunit 50 to the LCP, and also from the LCP over to the System 10.

(a) Disconnect from Main System 10: referring to FIG. 7C, at STC 6, whena "Read" instruction is specified in the Command Descriptor C/D, fromthe System, the READF (read flip-flop: located on the data flow card;the logic state of the read flip-flop is controlled by output levelsfrom the OP code register; the set state of READF indicates that a"Read" operation is being performed by the System) is set. The LCPenables setting of the LPW register 24_(w) to logic "1's", then steps toSTC 1, disconnecting from the System 10 to receive data from theperipheral terminal unit 50. The terminal bus multiplexor 24_(x2) (FIG.6D) select A level (SLARAM) is active, and SLBRAM, SLAIN and SLBINlevels are inactive to provide a path for data from the UART 31 over tothe LCP buffer 25₀₀.

(b) Receipt and Storage of Data from Terminal Unit: referring to FIG.7C, at STC 1, with READF set, the terminal start (TERST) level isactive. This TERST level causes the UART 31 to be master cleared andenables the setting of TERMACTF (terminal active flip-flop; located onterminal control card; the logic state of this flip-flop is controlledby TERST, TRECF and SENDF; the set state of TRMACTF indicates that theterminal control section of the LCP has been activated for a "Read" or a"Write" operation) to activate terminal control logic. READF alsoenables the setting of the terminal receive flip-flop (TRECF) to allowreceipt of data from the peripheral terminal unit 50. The buffer 25₀₀has its address preset to MADR location 255 and if the even flip-flop(EVNF) is not already set, its setting is enabled to initiate control ofbuffer addressing. Data characters are transferred serially from theperipheral terminal unit 50 to the UART 31 in the LCP, and the UARTchecks each character for even vertical parity.

(b-1) Receipt of First Character and Generation of Vertical Parity: withthe terminal receipt flip-flop (TRECF) set, and the data store flip-flop(DATASTF), in a reset state, receipt of the first character causes thedata received level (DR) to be active. The DR level enables setting ofthe reset UART flip-flop (RSUARTF) and also the terminal busy flip-flop(TRMBSYF). The even flip-flop, EVNF, is set, causing the buffer addressto be incremented to MADR location 0. The setting of the data storeflip-flop, DATASTF, and the resetting of EVNF are then enabled, inpreparation for storing the first character in the buffer. With RSUARTFset, the SLARAM level is generated which places the first character onthe AB digits and also on the CD digits of the terminal bus 47, forminga complete word. A parity bit is not included with this word. Thecontents of the terminal bus 47 are applied to the vertical paritygenerator/checker 48 of FIG. 6D. Parity for the word on the terminal bus47 is generated and a flip-flop, used to designate odd vertical parityis set or reset, as applicable to indicate parity, until receipt of asecond character from the peripheral terminal unit 50.

(b-2) Storage of First Character in Buffer: with the data storeflip-flop DATASTF set, the reset state of EVNF causes the buffer writeenable A (ERWA) level to be active. The System Write Enable (WESYS)level is also active, and these two levels provide the Write Enableinput for the AB and CD digits of the buffer network. The firstcharacter is then stored both in the AB and the CD digit locations ofMADR location 0 of Memory Address Register 36. Transfer of the firstcharacter from the UART 31 to the buffer 25₀₀ causes the reset UARTflip-flop (RSUARTF) to be reset. The data receive level (DR) is thenmade inactive, followed by the resetting of DATASTF (Data StoreFlip-Flop). This combination of logic prepares the UART 31 to accept thesecond character from the peripheral terminal unit 50.

(b-3) Receipt and Storage of Second Character: when the second characteris received by the UART 31, the data receive level (DR) is again madeactive and RSUARTF is set. This logic in combination with the resetstate of the even flip-flop EVNF inhibits the buffer address from beingincremented. The setting of the data store flip-flop DATASTF and theeven flip-flop EVNF are then enabled in preparation for storing thesecond character in the buffer. The terminal bus multiplexor selects Alevel, SLARAM, is still active and the character is placed on both theAB and the CD digits of the terminal bus 47. The contents of theterminal bus 47 are again applied to the vertical paritygenerator/checker 48. Parity is generated for the word on the terminalbus 47 and is compared with the parity generated during receipt of thefirst character. From the results of the comparison, a single parity bitis generated for the first and second characters.

With the data store flip-flop DATASTF and the even flip-flop EVNF set,the ERWB level (Write Enable level for CD digits of LCP buffer) isgenerated and the second character is stored in the last characterposition (CD digits) of buffer 25₀₀ at address location MADR 0,overwriting the character previously placed there. The character on theAB digits of the terminal bus 47 is not stored in the buffer 25₀₀because the ERWA level is not active (ERWA is the Write Enable level forthe AB digits of the LCP buffer). A parity bit from the vertical paritygenerator/checker 48 is added to the complete word now contained in theMemory Address Register at MADR 0.

(b-4) Receipt of Additional Characters and Start of Block CheckCharacter (BCC) Accumulation: additional characters are accepted by theLCP. With the receipt of each character, the logic state of the evenflip-flop EVNF is complemented to control incrementing of the MemoryAddress Register 36, so as to place data into the buffer 25₀₀ in wordformat. With the receipt of the "start of heading/start of text"character (SOH/STX) from the peripheral terminal unit 50, the blockcheck character register 33 of FIG. 6D is enabled and each characterfollowing the SOH/STX character is applied to the BCCR 33 to accumulatea block check character BCC for the message being received. Accumulationof a BCC will continue through receipt of the first buffer load of dataand through receipt of succeeding buffer loads of data until the endingcode (ETX character) is received. The actions that occur when an endingcode is received will be described subsequently hereinafter.

(c) Buffer Filled: when the LCP buffer 25₀₀ is completely filled withdata, the even flip-flop EVNF and the Memory Address MADR 252 level areset, enabling the setting of the buffer transfer flip-flop (BFXFRF). Thesetting of BFXFRF indicates that the LCP buffer 25₀₀ needs service, andthe LCP initiates a request for a reconnection to the System 10.

(d) Request for Reconnection to System 10: after disconnection, STC 1,the LCP initiates a request for a reconnection to the System by enablingthe setting of the LCP request flip-flop LCPRQF. The setting of the I/Osend flip-flop (IOSF) is enabled also, to condition the data lines fortransfer of data to the System 10, and the setting of the Memory AddressMADR 253 (FIG. 6C) is enabled to allow access to the Descriptor LinkD/L. The LCP then steps to STC 5 to send the Descriptor Link D/L and theLPW to the System 10.

The term MADR refers to Memory Address levels. These are generated onthe Terminal Control Card from outputs of the Memory Address Register36. These levels represent address locations, shown in Table XI, in theLCP buffer 25₀₀ (FIG. 6C) which are reserved for the following:

                  TABLE XI                                                        ______________________________________                                        Location      Description                                                     ______________________________________                                        251           Next-to-last data word                                          252           Last data word                                                  253           Descriptor link information word                                254           Descriptor link information word                                255           Descriptor link LPW                                             ______________________________________                                    

When one of the eight LCP address levels, LCPADn, isreceived from theassociated Distribution Card 20_(0d) during the reconnection sequence,then the LCP address level, LCPADL, is active. The LCPADL address levelis generated on the Terminal Control Card when the applicable LCPADnlevel is active. The LCPADn level also generates the gate system level,GATSYS, to enable the LCP backplane network. The LCP connected (LCPCON)level is sent to the Distribution Card 20_(0d) to indicate that the LCPis reconnected. The SLAIN level is active and the SLBIN, SLARAM, and theSLBRAM levels are inactive in order to allow the Descriptor Link D/L tobe transferred to the Latch Register 49 (FIG. 6D).

(e) Transfer of Descriptor Link D/L and the Descriptor Link LPW: in FIG.7C, at STC 5, the transmit flip-flop (XMITF) is set. The transmitflip-flop is located on the System Logic card and the set stateindicates that the LCP is transferring data to the System 10, thus,activating the "read" module of the LCP. LCP transfers the DescriptorLink D/L and the longitudinal parity word LPW (previously received atSTC 6) back to the System 10. The LCP then enables setting of the LPWregister 24_(w) to logis "1's", and steps to STC 4 to transfer data tothe System 10.

(f) Transfer of Data to System 10: at STC 4 of FIG. 7C, the transmitflip-flop XMITF and the I/O send flip-flop, IOSF, are still in the "set"state from the operation at STC 5. The asynchronous strobe flip-flop(ASYNCF) is set to enable asynchronous transfer of data to the System10. Data is transferred from the LCP buffer 25₀₀, by way of the datalatch register 49 (FIG. 6D) to the System 10 (via the system interface22_(si) of FIG. 6C). Transfer is accomplished one word (plus a paritybit) at a time. The LCP strobe level LCPSTL accompanies the transfer ofeach word, and as each word is received by the System 10, the Systemsends a strobe pulse to acknowledge receipt of a word. Each word placedon the terminal bus 47 of FIG. 6D for transfer to the System 10 isapplied simultaneously to the latch register 49 and the LPW register24_(w). The LPW register 24_(w) accumulates the longitudinal parity wordLPW during the data transfer. When the last data word address of the LCPbuffer 25₀₀ (MADR 252) is attained, the synchronous flip-flop (SF, whichis located on the Terminal Control Card and is set when the LCP is alsotransferring data to the peripheral terminal unit) is set, resulting inthe development of the synchronous level, SFL, and then the LCP stepsover to STC 12 to send an LPW to the System 10.

(g) Transmission of Longitudinal Parity Word to System 10: in FIG. 7C atSTC 12, the LPW accumulated in the LPW register 24_(w) during operationat STC 4, is sent to the System 10. The LCP then enables setting of theLPW register 24_(w) to logic "1's" and steps to STC 1 to receiveadditional data from the peripheral terminal unit 50 (via the terminalunit device interface 22_(di) of FIG. 6C). After this, the LCP steps toStC 5 to send a Descriptor Link to the Main System 10.

(h) Receipt of Additional Data and Ending Code from Peripheral TerminalUnit: upon the second entry to STC 1, a terminal active flip-flop(TRMACTF) and a terminal receive flip-flop (TRECF) are both in a setstate from the previous operation at STC 1. The terminal receiveflip-flop TRECF is located on the terminal control card and thisflip-flop is set when the LCP is receiving data from the peripheralterminal unit; the terminal active flip-flop, TRMACTF, is also locatedon the terminal control card and, in its set state, indicates that theterminal control section of the LCP has been activated for a "Read" or"Write" operation. The LCP buffer address is again set to MADR 255 inpreparation for receipt of data from the peripheral terminal unit 50. AtSTC 1, the actions of the LCP while receiving the second buffer load ofdata from the peripheral terminal unit 50 are the same as thoseperformed during the receipt of the first buffer load, up to the pointthat an ending code is received on the terminal bus 47.

Assuming that prior to receipt of the end code, at STC 1, that thefollowing two conditions exist: (1) EVNF is reset, indicating that thenext character to be received will be placed in the last characterposition (CD digits) of a word; and (2) both RSUARTF (Reset UARTFlip-Flop) and the data store flip-flop (DATASTF) are reset. When theending code character is received, RSUARTF is set, providing thenecessary logic level to generate the Write Enable (ERW 18) level forthe ending code RAM. Receipt of an ending code is recognized by the LCPwhen the character is on the terminal bus 47. Recognition of the endingcode causes the end code level, EDCODE, to be generated, which developsthe data input level (RAM 18 L) for the ending code RAM; the end-flagbit (ENDFG) is then stored in the present buffer address of the buffer25₀₀. The setting of EVNF and DATASTF is then enabled, which conditionsthe LCP to store the ending code in the buffer 25₀₀. With EVNF set, theERWB (Write Enable level for CD digits) level is active and thecharacter is stored in the last character position of the same wordaddress in which the end-flag level, ENDFG, is stored.

(i) Check of BCC and Request for Reconnection to System 10: with DATASTFset, the EDCODE level enables the setting of the end flip-flop (ENDF).The LCP now receives a block check character (BCC) from the peripheralterminal unit 50 and checks it against the accumulated BCC in the blockcheck character register 33. The setting of the end flip-flop ENDFcauses the terminal receive flip-flop TRECF to be reset, and theterminal complete level (TMCMP) to be active, terminating the actions ofthe terminal control section of the LCP. The LCP then initiates arequest for a reconnection to the System and steps from STC 1 to STC 5to send the Descriptor Link D/L to the System 10.

(j) Transfer of Descriptor Link D/L and the Descriptor Link LPW: as inthe preceding reconnection to the System, at STC 5 the LCP sends theDescriptor Link D/L and the LPW to the System, and then steps to STC 4(Read) to transfer data to the System 10.

(k) Transfer of Data to System 10: at STC 4, the actions of the LCP arethe same as described before at STC 4, until the word containing theending code character is placed on the transfer bus for transfer to theSystem 10. Recognition of the ending code causes the System end level(SYSEND) to be developed, and the LCP steps to StC 12 to send an LPW tothe System 10.

(1) Transmission of LPW and Result Descriptor R/D to System 10: the LCPsends the LPW accumulated in the LPW register 24_(w) to the System 10.After the LPW is sent, since the terminate complete level (TMCMP) is nowactive, indicating that there is no more data to be transferred, the LCPsteps to STC 7 to send a Result Descriptor R/D to the System 10.

At STC 7, the LCP sends a Result Descriptor R/D to the System 10, thensteps to STC 15 (FIG. 7D), and sends an LPW, then returns to idle at STC3 to await another instruction from the System 10.

The above discussion has involved the general flow path for a "Read"operation in which more than one buffer load of data was transferredfrom a peripheral to the Main System, and in which the operation wasconcluded by receipt of an ending code.

However, during a "Read" operation, other situations may occur to causealternate logic flow paths and the handling of possible errorconditions. The following sections (a) through (d) indicate the actionsof the LCP when modifications to the original "Read" instructions aremade either by the System 10 or by the LCP:

(a) Receipt of Time-Out Level: referring now to FIG. 7E, which is madeof two sheets, 7E-1 and 7E-2; at STC 1, with operation of the one-secondtimer not inhibited, and data being received by the LCP from theperipheral terminal unit 50; if the sending of data is interrupted for aperiod of one second, the time-out level (TIMOUTL) is generated. WithTIMOUTL active, the end flip-flop (ENDF) is set, and the terminalcomplete level (TMCMP) is generated. A request for reconnection to theSystem 10 is initiated and the LCP steps over to STC 5. At STC 5, withthe end flip-flop (ENDF) set, the Read operation is terminated and theLCP steps over to STC 7 to send a Result Descriptor R/D to the System10. A time-out level can also be received with the LCP at STC 3 as canbe seen in FIG. 7E at STC 3 "idle status".

(b) Transmission Still Expected from Peripheral Terminal Unit: in FIG.7E, at STC l, with the LCP conditioned to receive data from theperipheral terminal unit 50, then if data is not being received, the LCPsteps immediately to STC 3 in order to be in a condition to receive aconditional cancel instruction from the System 10. The LCP will returnfrom STC 3 over to STC 1 if a data transmission begins. (c) Request forEmergency Reconnection: during transfer of data from the peripheralterminal unit 50 to the LCP, when the buffer 25₀₀ is completely filled,a buffer transfer flip-flop (BFXFRF) is set, initiating a request for areconnection to the System 10 to store data. (The buffer transferflip-flop (BFXFRF) is set when the LCP buffer 25₀₀ is filled with datafrom the peripheral terminal unit 50, or when emptied during transfer ofdata from the LCP to the peripheral terminal unit). If a reconnection isnot completed prior to the time the UART 31 receives another character,the emergency request level (EMRREQ) is generated. The EMRREQ level issent to the associated Distribution Card 20_(0d) to initiate anemergency request for a reconnection to the System 10.

(d) Receipt of Ending Code (AB digits): the actions of the LCP relatingto receipt of an ending code, which will be placed on the AB digits(first character) of a word, are more varied than those involved withreceipt of an ending code to be placed on the CD digits of a word. Thiscondition exists because a transmission from the peripheral terminalunit may consist of data followed by an ending code, or it may consistmerely of an ending code by itself. Additionally, decrementing of theSystem Memory Address may or may not be required when storing the endingcode, in order to reflect the accurate location of the ending code inSystem Memory 10_(m). Thus, the following actions of the LCP for thesevarious conditions are discussed below in paragraphs d1 and d2:

(d1) Receipt of Ending Code Following Data: if the ending code follows aseries of data characters and is received on the terminal bus 47 whenthe even flip-flop (EVNF) is set, the character, when stored, will beplaced in the AB digit position of a word in the LCP buffer 25₀₀. Whenthe character is received, the end code level (EDCODE) is generated,causing RAM 18 L (Write end-flag level) to be active, and the end-flaglevel (ENDFG) is stored in the presently current buffer address. (Theend code level (EDCODE) is generated on the terminal control card whenan end code character is in the A and B digits of the terminal bus 47.The end-flag level, ENDFG, is generated on the data flow card from RAM18 L, and when active, this level identifies the address of an end codein the LCP buffer 25₀₀. The write end-flag level (RAM 18 L) is the datainput level for the end-flag RAM of the LCP buffer 25₀₀). The set stateof the even flip-flop (EVNF) then causes the buffer address to beincremented to the next word address. The setting of the data storeflip-flop (DATASTF) and the complementing of the even flip-flop (EVNF)are then enabled. With EVNF reset, the write enable A (ERWA) level isgenerated and the ending code is stored in the AB digits of the bufferaddress following the one in which the end-flag level (ENDFG) wasstored. The LCP then initiates a request for reconnection to the MainSystem to transfer data and the ending code to the System 10.

During transfer of final data from the LCP buffer 25₀₀ to the System 10at STC 4, an ending code in the AB digits of a word will be recognizedwhen ENDFG (end-flag level) level is active and the system end codelevel (SYSEND) is inactive. This logic combination indicates that thenext word to be transferred contains an ending code in the AB digits. InFIG. 7E, the LCP steps to STC 14 to accomplish transfer of a singlecharacter. At STC 14 the setting of a word transfer control flip-flop(WTCF) is enabled uncoditionally. The setting of the character transferflip-flop (CTSF) is enabled to specify that the character transfer statewas entered. The ending code is stored in System Memory 10_(m), and theLCP steps first to STC 12 to send a longitudinal parity word LPW to theSystem 10, then steps over to STC 7 to send a Result Descriptor R/D tothe System 10.

(d2) Receipt of Ending Code Only: as per FIG. 7E, at STC 1, if thetransmission from the peripheral terminal unit 50 consists of a singlecharacter (end code), it will be received on the terminal bus 47 withthe even flip-flop EVNF in a set state, and will be placed on the ABdigit position of a word in the LCP buffer 25₀₀. The character is storedand the LCP initiates a request for reconnection to the System totransfer the character, as seen in the 3rd block of FIG. 7E at STC 5.This steps over to STC 4, and with the end code level (EDCODE) active,the setting of the character end flip-flop (CHARENF) is enabled. Thecharacter is transferred (STC 14) to the System 10 and the LCP stepsover to STC 12 to send a longitudinal parity word (LPW) to the System10. At STC 12, the set state of CHARENF (the character end flip-flop)causes the LCP to step directly to STC 9 to initiate decrementing of theSystem Memory Address 10_(m) . Then the LCP steps to STC 7 in order tosend a Result Descriptor R/D to the System 10.

(e) Receipt of Terminate Signal from System: a terminate signal (TERMlevel) is sent from the System to the LCP during a Read operationwhenever available system memory space designated for the LCP operationis to be exceeded. During a Read operation, the TERM level may bereceived (FIG. 7E) at STC 4, STC 14, or STC 12. The actions of the LCPupon receipt of the TERM level depend upon the status count in which theLCP is operating when the TERM level is received, and upon whether ornot the receipt of the TERM level is preceded by the receipt of anending code character from the peripheral terminal unit 50. Under theseconditions, the actions of the LCP are discussed in the followingparagraphs e1 and e2:

(e1) Receipt of Terminate Signal Before Ending Code is Received: if theLCP receives the TERM (terminate signal) level from the System before ithas sufficient time to receive and store an ending code, the LCP thenacts as follows:

e1 (a) The receipt of the TERM level while the LCP is transferring datato the System at STC 4, causes the terminate flip-flop (TERMF) to beset, and the LCP steps over to STC 12. A longitudinal parity word LPW issent to the System 10 and the set state of the terminate level (TERMF)causes the LCP to terminate the Read operation and step over to STC 7 tosend a Result Descriptor R/D to the System 10.

e1 (b) In FIG. 7E, the LCP steps from STC 4 over to STC 12 aftertransferring a word containing an ending code in the CD digits over tothe System 10. If the TERM level is now received at STC 12, the settingof the word transfer control flip-flop (WTCF) is enabled, and the LCPremains in STC 12 for an additional strobe time. If during the secondstrobe time, the TERM level is still active, this indicates that theending code was not transferred. The setting of TERMF (terminateflip-flop) is enabled and the LCP steps over to STC 7 to send a ResultDescriptor R/D to the System 10.

e1(c) The LCP steps from STC 4 over to STC 12 when the last word in thebuffer 25₀₀ has been transferred. If the TERM level is now received atSTC 12, the LCP remains in STC 12 for additional strobe time. The wordtransfer control flip-flop (WTCF) is set and regardless of the logicstate of the TERM level during the second strobe time, the LCPterminates the Read operation and steps over to STC 7 to send a ResultDescriptor R/D to the System 10.

e1 (d) The LCP will be in STC 14 if the last data word transferred atSTC 4 is to be followed by an ending code in the AB digits of the nextword. If the terminate (TERM) level is now received at STC 14, theending code is not stored and the LCP steps to STC 12, it sends an LPWto the System, and then steps to STC 7 to send a Result Descriptor R/Dto the System 10.

(e2) Receipt of Terminate Signal After Ending Code is Received: if theLCP receives the terminate level (TERM) from the System 10 after anending code has been received from the peripheral terminal unit 50, thenthe LCP acts as shown in the following paragraphs e2 (a), e2 (b), e2(c):

e2 (a) In FIG. 7E, the LCP steps from STC 4 over to STC 12 aftertransferring a word containing an ending code in the CD digits to theSystem 10. If the TERM level is now received at STC 12, the setting ofthe word transfer control flip-flop (WTCF) is enabled and the LCPremains in STC 12 for an additional strobe time. If during the secondstrobe time, the TERM level is no longer active, this indicates that theending code was transferred. The LCP then steps over to STC 7 to sendthe Result Descriptor R/D to the System 10.

e2 (b) The LCP steps from STC 4 over to STC 14 if the last wordtransferred at STC 4 is to be followed by an ending code in the ABdigits of a word. If the LCP progresses through STC 14 without receivingthe TERM level, the ending code is transferred to the System 10, and theLCP steps over to STC 12 to send a longitudinal parity word LPW. If theTERM level is now received at the STC 12, the LCP takes no action uponits receipt, but steps to STC 7 to send a Result Descriptor R/D to theSystem 10.

e2 (c) If a transmission from the peripheral terminal unit 50 consistsof a single character (ending code), then at STC 4, the LCP enables thesetting of the character end flip-flop (CHARENF) and steps over to STC12 to send a longitudinal parity word LPW. At STC 12, if the TERM levelis now received, the LCP will remain in STC 12 for an additional strobetime. If during the second strobe time, the TERM level is still active,this indicates that only the first half of the word containing theending code was transferred and the System Memory Address was notincremented to the next word address. The LCP steps over to STC 7 tosend a Result Descriptor R/D to the System 10. If the TERM level isinactive during the second strobe time, this indicates that the SystemMemory Address was incremented to the next word address and requiresdecrementing. The set state of the character end flip-flop (CHARENF) andthe inactive state of the terminate level (TERM) cause the LCP to stepover to STC 9 to initiate decrementing of the System Memory Address.From STC 9, the LCP steps over to STC 7 to send a Result Descriptor R/Dto the System 10.

Error Conditions: During the course of a "Read" operation, certain errorconditions may occur which will be acted upon by the LCP, as follows:

(a) Access Error: after transmitting the emergency request (EMRREQ)level, if the LCP has not received a reconnection to the System 10 priorto receiving a second character in the UART 31, the UART 31 generates alevel called overrun error level (OE). The OE level causes the enablingof the access error flip-flop (ACCERF) and of the end flip-flop (ENDF).The LCP then initiates a request for reconnection to the System 10 toterminate the Read operation and to send an error Result Descriptor R/Dto the System 10.

(b) Terminal Vertical Parity Error: during transfer of data from theUART 31 to the LCP buffer 25₀₀, if the parity error level (PE) isgenerated by the UART 31, the terminal vertical parity error flip-flop(TVPERF) is set to indicate existence of a vertical parity error. Thisflip-flop, TVPERF, has a logic state which is controlled by an outputfrom the LCP vertical parity generator/checker 48, or from the parityerror output of the UART 31 (FIG. 6D). The set state of the flip-flopindicates that a vertical parity error occurred during transfer of databetween the LCP and the peripheral terminal unit 50. This flip-flop islocated on a Terminal Control Card.

(c) Block Check Character Error: during the transfer of data (FIG. 6D)from the UART 31 to the LCP buffer 25₀₀, if the block check character OKlevel (BCCOK) is not active after the block check character has beenchecked, the block check character error flip-flop (BCCERF) is set toindicate the existence of a block check character error. The BCCOK levelis provided by decoder 34 of the block check character register 33 inFIG. 6D.

Write Flip-Read Operation:

This operation is essentially a Write operation followed by a Readoperation. Basically the previous discussion regarding the "Write"operation and the "Read" operation of FIGS. 7B and 7C are applicablehere. The receipt of a Command Descriptor C/D for the "write flip read"operation into the OP code and the variant registers 42 and 43 (FIG. 6D)respectively, causes a "Write" operation to be initiated and a FLIPlevel (Flip Level) to be generated. Data is transferred from the System10 to the peripheral terminal unit 50 during the "Write" portion of theoperation. When an ending code is recognized on the terminal bus 47during data transfer from the LCP to the peripheral terminal unit 50 atSTC 1 (FIG. 7C), then the end code level (EDCODE) is generated. TheEDCODE level enables the setting of the end flip-flop (ENDF) indicatingthat the data transfer is complete. The set state of the end flip-flop(ENDF) and the generation of the FLIP level enable the setting of theread flip-flop (READF), the terminal receive flip-flop (TRECF), and theeven flip-flop (EVNF), the resetting of the write flip-flop (WRITF), theterminal busy flip-flop (TRMBSYF), and the presetting of the bufferaddress to MADR 255. With these actions, the LCP is conditioned toreceive data from the peripheral terminal unit 50, without reconnectingto the System 10 to receive additional instructions.

To initiate the "Read" portion of the Write-Flip-Read operation, the LCPdoes not reconnect to the System 10. As per FIG. 7E, from StC 1, the LCPsteps over to STC 3 to await a transmission from the peripheral terminalunit 50. Receipt of the first character from the peripheral terminalunit 50 causes the DR level (Data Received) in the UART 31 to be active,enabling the setting of the reset UART flip-flop (RSUARTF) and theterminal busy flip-flop (TRMBSYF). The setting of the terminal busyflip-flop causes the LCP to return to STC 1 to receive the data. The"Read" operation progresses through to completion, subject to the sameconditions discussed previously for a regular Read operation.

Test Operation: The "test operation" provides the System 10 with thecapability for determining the operational status of the LCP withoutrequiring a transfer of data to or from the System Memory 10_(m).Located on a data flow card is a test flip-flop (TESTF). The logic stateof this flip-flop is controlled by output levels from the OP coderegister 42, FIG. 6D. The set state indicates that a test instructionwas received from the System 10. In FIG. 7E, at STC 11, with the testflip-flop (TESTF) set, the LCP has no requirement to step to STC 6 toreceive a Descriptor Link D/L. It steps instead to STC 7 to return aResult Descriptor R/D to the System 10. From STC 7, the LCP steps overto STC 15, and then STC 3 (idle), where it remains until another CommandDescriptor C/D is received. Under normal conditions, the ResultDescriptor R/D sent to the System 10 for a "test operation" will haveall bits equal to zero. The System 10 will recognize, by this condition,that the LCP is operational. Test Enable Operation: The receipt of aCommand Descriptor C/D containing a "test enable" instruction conditionsthe LCP so that the peripheral terminal unit 50 can initiate acommunication with the System 10. The peripheral terminal unit 50initiates a request for communication by sending an inquiry character(ENQ) to the LCP. Upon receipt of the inquiry character (ENQ), the "testenable" operation is terminated and the System initiates a "Read"operation to receive data from the peripheral terminal unit 50. If theterminal unit sends any other character but an ENQ inquiry character,the character will not be recognized and the LCP will take no action.The "test enable" operation operates (in reference to FIG. 7E) asfollows:

At STC 3, upon receipt of a "test enable" instruction, the variantregister flip-flop No. 3 (VAR3F) is set. The "VAR (1-4) F" representsthe 4 variant register levels. These are generated on the Data Flow Cardby outputs of the variant register 43, FIG. 6D. The logic state of theselevels is dependent upon the numerical value contained in the variantdigit 1 of the Command Descriptor C/D. The setting of VAR3F inhibits thesetting of the test flip-flop (TESTF) but allows the read flip-flop(READF) to be set. The LCP steps over to STC 11 to receive the CommandDescriptor longitudinal parity word LPW from the System 10, and thensteps over to STC 6 to receive the Descriptor Link D/L from the System.At STC 6, because the "Read" flip-flop (READF) is set, the LCPdisconnects from the System 10 and steps over to STC 1 to receive aninquiry character (ENQ) from the peripheral terminal unit 50. At STC 1,(unless an inquiry character (ENQ) is received immediately) the LCPsteps over to STC 3 to await a transmission from the peripheral terminalunit 50. When the terminal unit transmits, the terminal busy flip-flop(TRMBSYF) is set, causing the LCP to step over to STC 1 to receive theinquiry character (ENQ). When the ENQ is received, the set state of thevariant register level, VAR3F, inhibits the LCP from stepping over toSTC 4 and also inhibiting the transfer of the character to the System10. Instead the LCP steps over to STC 7 to return a Result DescriptorR/D to signify to the System 10 that the " test enable" operation iscomplete.

Conditional Cancel Operation: The "conditional cancel operation"provides the System 10 with a capability to cancel a previously sentCommand Descriptor C/D containing a "Read" operation. Referring to FIG.7E, if the LCP has initiated a "Read" or a "Write flip Read" operation,but the expected data transfer from the peripheral terminal unit 50 isnot in progress, the LCP will remain at STC 3 awaiting a possible"conditional cancel" instruction. If a conditional cancel instruction isnow received, the "Read" operation is cancelled and the cancel flip-flop(CANCF) is set. This cancellation will not be effectuated unless the LCPis at STC 3. The LCP then steps over to STC 11 to receive a CommandDescriptor longitudinal parity word LPW from the System 10. The setstate of the cancel flip-flop CANCF inhibits the LCP from stepping toSTC 6. Instead, the LCP steps over to STC 7 to return a ResultDescriptor R/D to the System 10, indicating that the conditional canceloperation is completed.

Echo Operation: The "echo operation" is a maintenance aid to troubleshooting of the LCP. This operation begins with a "Write" operation inwhich data is transferred from System Memory 10_(m) over to the LCPbuffer 25₀₀. This is followed by a "Read" operation in which the samedata is transferred back to System Memory 10_(m). Assuming, for example,that less than a full buffer load of data will be transferred and thatthe operation will be terminated by receipt of an ending code in thelast character position of a word; and since the "echo operation" isessentially a Write operation followed by a Read operation, thefollowing discussion will involve only those LCP actions which areunique to the echo operation. (Read and the Write operations werepreviously discussed in connection with FIGS. 7B and 7C). Now referringto FIG. 7E, at STC 6, and with the echo flip-flop (ECHOF) set, the LCPsteps over to STC 8 to accept data from the System 10. Beginning at STC8, the LCP operates as previously discussed during a regular "Write"operation up to the point that the LCP receives an ending code and thensteps over to STC 12. At STC 12, although no data is to be transferredfrom the LCP to the peripheral terminal unit 50, the LCP disconnectsfrom the System 10 by stepping momentarily over to STC 1. Whendisconnected at STC 1, the LCP initiates a request for reconnection tothe System 10 by enabling the setting of: the LCP request flip-flop(LCPRQF); the I/O send flip-flop (IOSF); and by the presetting of thebuffer address to MADR 253 (Descriptor Link, FIG. 6C). The LCP thensteps over to STC 5 to send the Descriptor Link D/L to the System 10. AtSTC 5, the LCP transfers the Descriptor Link D/L to the System 10. Theset state of the echo flip-flop (ECHOF) then causes the LCP to step overto STC 4 to return data in the buffer 25₀₀ back to the System Memory10_(m). Beginning at STC 4, data is transferred from the LCP over to theSystem 10. The actions performed by the LCP are as those previouslydescribed during a regular "Read" operation up to the point that the LCPidentifies an ending code on the terminal bus 47 and then steps over toSTC 12. At STC 12, the Read operation is completed and the set state ofthe echo flip-flop (ECHOF) causes the LCP to step over to STC 7 toreturn a Result Descriptor R/D over to the System 10. Return of ResultDescriptor R/D: FIG. 7D is a simplified logic flow diagram regarding thereturn of the Result Descriptor R/D. The LCP steps over to STC 7 toreturn a Result Descriptor R/D to the System 10 under any of thefollowing conditions listed as a, b, c, d:

a. At STC 12 or STC 9 when a "Read" or an echo operation is completed.

b. At STC 5 when a "Write" operation is completed.

c. At STC 11 when any one of the following conditions occur:

(c1) A descriptor error occurred; (c2) A test operation is specified bythe Command Descriptor C/D being executed;

(c3) The conditional cancel flip-flop (CANCF) is set.

d. At STC 6 if a vertical or longitudinal parity error has occurred.

At STC 7, if the transmit flip-flop (XMITF) is not set, it is set atthis time to activate the LCP Read module. The terminal bus multiplexorselect A level (SLARAM) and the terminal bus multiplexor select B level(SLBRAM) are both active, which allows the terminal bus multiplexornetwork (24_(x2) of FIG. 6D) to select a word made up of ResultDescriptor levels for transmission to the System 10. When the ResultDescriptor word is placed in the data latches, 49, it is also applied tothe LPW register 24_(w) to generate an LPW for the Result Descriptortransfer. The LCP then steps over to STC 15 to send the R/D LPW to theSystem 10.

At STC 15, the terminal bus multiplexor select A level (SLARAM) isinactive and the terminal bus multiplexor select B level (SLBRAM) isactive, which allows the terminal bus multiplexor network (24_(x2) ofFIG. 6D) to select outputs of the LPW register 24_(w) for transmissionto the System 10. (The SLBRAM) is used in conjunction with the SLARAM toselect one of four inputs to the terminal bus multiplexor network).These are generated on the System Logic Card from outputs of the STCdecoder 54 of FIG. 6D. The LCP transfers the LPW, resets selected logiclevels to a beginning state, and then steps over to STC 3. The LCPremains at STC 3 until another Command Descriptor C/D is received. Insummary the LCP operates in two "modes"--the "off-line" mode and the"on-line" mode.

Off-line mode:

Operation of the LCP/Terminal Unit combination in an off-line mode isfor the purpose of performing maintenance functions. In the field, avariety of operations can be performed to verify the condition of theLCP or for simple trouble shooting. These operations can be carried outwithout effecting the normal operation of other LCP's in the same BaseModule.

On-line mode:

The two basic operations controlled by the LCP in the on-line modeoperations are (1) a Write operation in which data is received from theSystem by the LCP and which data is transferred to the peripheralterminal unit; and (2) a Read operation in which data is received fromthe terminal unit by LCP and is transferred to the System Memory 10_(m).

In addition to these basic operations, the LCP can change from a "Write"to a "Read" operation with a single instruction, and can also performselected test operations. The following items represent the specificoperations which the LCP can perform by means of program instructionsfrom the Main System 10. This is done by means of Command Descriptors(C/D) and herein follows a brief summary of what is accomplished by eachoperation.

Table XII here below summarizes the specific operations which the LCPcan perform:

                  TABLE XII                                                       ______________________________________                                        a. Write           d. Test                                                    b. Read            e. Test Enable                                             c. Write Flip Read f. Conditional Cancel                                                         g. Echo                                                    ______________________________________                                    

Command Descriptors:

The Command Descriptors (C/D) are instructions from the Main System 10to the LCP regarding certain operations to be performed. The followingitems will summarize briefly the Command Descriptors associated witheach of the instructions (of Table XII) from the Main System 10:

(a) Write:

The "Write" Command Descriptor is an instruction to transfer data fromSystem Memory 10_(m) to the peripheral terminal unit desired, forexample, such as peripheral terminal unit 50. The LCP accepts data fromthe System 10 until the LCP buffer 25₀₀, for example, is full, or untilthe data transfer is stopped by the receipt of an "ending code" or a"terminate" signal from the Main System 10. When the LCP buffer 25₀₀ isfull, or when an "ending code" is received, the LCP transfers thecontents of the buffer 25₀₀ to the peripheral terminal unit 50. The"Write" Command Descriptor is identified as shown in Table XIII below:

                  TABLE XIII                                                      ______________________________________                                        (Write C/D)                                                                   Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 1                                                          A2                 0  OP Digit                                                A1                 0                                                          B8                 0                                                          B4                 0                                                          B2                 0  Variant Digit 1                                         B1                 0                                                          ______________________________________                                    

(b) Read: The "Read" Command Descriptor is an instruction to transferdata from the peripheral terminal unit involved, such as unit 50, overto the System Memory 10_(m). The LCP first accepts data from theperipheral terminal unit 50 until the LCP buffer 25₀₀ is full, or untilthe data transfer is stopped by the receipt of an "ending code" from theperipheral terminal unit. When the LCP buffer 25₀₀ is full, (or when theending code is received), the LCP transfers the contents of the buffer25₀₀ over to the System Memory 10_(m), unless the Main System 10 sends a"terminate" signal to stop the Read operation because System Memoryspace is not available to store any more data. If, after initiating aRead operation, the LCP receives no data for a period of one second, theLCP "times out" and sends a Result Descriptor (R/D) to the Main System10. The one-second timing interval can be inhibited by setting a bit(B1) of the variant digit 1 of the Command Descriptor equal to 1. TableXIV below shows the "Read" C/D.

                  TABLE XIV                                                       ______________________________________                                        (Read C/D)                                                                    Data Lines         Digit Value                                                ______________________________________                                        A8                 1                                                          A4                 0                                                          A2                 0  OP Digit                                                A1                 0                                                          B8                 0                                                          B4                 0                                                          B2                 0  Variant Digit                                           B1                 see                                                                           note                                                       If B1 is equal to 1, the one-second time-out period,                          allowed to the terminal unit to respond, is inhibited.                        ______________________________________                                    

(c) Write flip Read:

The "Write flip Read" Command Descriptor is an instruction to the LCP toaccomplish a Write operation, at the conclusion of which an immediateRead operation is performed without any intervention from the MainSystem 10. Data is accepted from the Main System 10 and transferred tothe peripheral terminal unit until an "ending code" is received. Uponreceipt of the ending code from the Main System 10, the LCP transfersthe ending code to the peripheral terminal unit and then changes to theRead Mode. The LCP then accepts data from the peripheral terminal unitand transfers it to the System Memory 10_(m) until an ending code isreceived from the peripheral terminal units, or until a terminate signalis received from the Main System 10. If, after beginning of the Readportion of the operation, the LCP receives no data for a period ofone-second, then the LCP "times-out" and sends a Result Descriptor (R/D)to the Main System 10. Of course, the one-second time interval can beinhibited if desired, by setting the bit B1 of the variant digit 1 ofthe Command Descriptor equal to one. Table XV below illustrates the"Write flip Read" Command Descriptor.

                  TABLE XV                                                        ______________________________________                                        (Write flip Read C/D)                                                         Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 1                                                          A2                 0  OP Digit                                                A1                 0                                                          B8                 1                                                          B4                 0                                                          B2                 0  Variant Digit                                           B1                 see                                                                           note                                                       If B1 is equal to 1, the one-second time-out period,                          allowed to the terminal unit to respond, is inhibited.                        ______________________________________                                    

(d) Test:

The "test" Command Descriptor is an instruction to the LCP to indicateits "operational status" by returning a Result Descriptor (R/D) to theMain System 10. If the LCP is present and available, the ResultDescriptor will be equal to all "0's". Table XVI below shows the TestCommand Descriptor:

                  TABLE XVI                                                       ______________________________________                                        (Test C/D)                                                                    Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 0                                                          A2                 1  OP Digit                                                A1                 0                                                          B8                 0                                                          B4                 0                                                          B2                 0  Variant Digit 1                                         B1                 0                                                          ______________________________________                                    

(e) Test Enable:

The "test enable" Command Descriptor is an instruction to the LCP tomonitor incoming data from the peripheral terminal unit, and uponreceipt of an Inquiry Character (ENQ), to form and transmit a ResultDescriptor (R/D) to the System 10. This instruction is used to allow theperipheral terminal unit to initiate a communication with the MainSystem 10. Table XVII below illustrates this Command Descriptor.

                  TABLE XVII                                                      ______________________________________                                        (Test Enable C/D)                                                             Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 0                                                          A2                 1  OP Digit                                                A1                 0                                                          B8                 0                                                          B4                 1                                                          B2                 0  Variant Digit                                           B1                 see                                                                           note                                                       ______________________________________                                         Note:                                                                         If B1 is equal to 1, the onesecond timeout period, allowed to the termina     unit to respond, is inhibited.                                           

(f) Conditional Cancel:

The "Conditional Cancel" Command Descriptor is an instruction to the LCPto initiate cancellation of another Command Descriptor under certainconditions. When the Conditional Cancel Command Descriptor is receivedby the LCP, and, if data is not being received from the peripheralterminal unit during the applicable portion of a Read operation, thenthe previous Command Descriptor will be cancelled. This C/D is shown inTable XVIII:

                  TABLE XVIII                                                     ______________________________________                                        (Conditional Cancel C/D)                                                      Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 0                                                          A2                 1  OP Digit                                                A1                 0                                                          B8                 1                                                          B4                 0                                                          B2                 0  Variant Digit 1                                         B1                 0                                                          ______________________________________                                    

(g) Echo:

The "Echo" Command Descriptor is an instruction to the LCP to accept afull buffer of data (or less) from the Main System 10 and then to returnthe same data back to the Main System 10 to be stored. This provides amaintenance check and trouble shooting diagnosis cycle for theSystem-LCP operations. Table XIX illustrates this Echo CommandDescriptor.

                  TABLE XIX                                                       ______________________________________                                        (Echo C/D)                                                                    Data Lines         Digit Value                                                ______________________________________                                        A8                 0                                                          A4                 0                                                          A2                 0  OP Digit                                                A1                 1                                                          B8                 0                                                          B4                 0                                                          B2                 0  Variant Digit 1                                         B1                 0                                                          ______________________________________                                    

The above specification has described and illustrated the basic elementsand configuration of an Input-Output Subsystem which, working incoordination with a main host system and its IOT interface uses aplurality of I/O processors (LCP's) organized in Base Module units whichcan efficiently and accurately execute and control data transferoperations between specific peripheral devices and the main system toprovide a high bandpass and minimize access errors. The following claimsare made

What is claimed is:
 1. In a system involving a plurality of remoteperipheral terminal units at remote stations, each peripheral terminalof which is connected to its own specific peripheral-controller, saidperipheral-controllers being organized into groups designated as basemodules at each remote station, and wherein each base module has its ownmessage level interface bus connecting it, via main system interfaceunit, to a central main system comprising a processor and main memory,an input-output subsystem comprising:(a) a main system interface unitconnected between said main system and a plurality of base moduleshousing a plurality of peripheral-controllers, said main systeminterface unit including:(a1) means to formulate an I/O task command anda Descriptor-Link Word to identify a particular data transfer task for aparticular peripheral-controller, said task command and Descriptor-LinkWord being communicated to a specific peripheral-controller; (a2) meansto determine the highest priority signal code from competingperipheral-controllers which are requesting access to main memory and togrant connecting access to main memory to the highest priority codedperipheral-controller; (a3) means to connect or disconnect main memoryto an addressed peripheral-controller; (a4) means to asynchronouslytransfer data between main memory and an addressedperipheral-controller; (a5) means to store addresses and address countsfor data transfers occurring between main memory and a connectedperipheral-controller, said main system interface unit operatingindependently of said main processor for data transfers with said mainmemory; (a6) means to receive a result descriptor word from a peripheralcontroller, said result descriptor word representing the completion,incompletion or error-status of an I/O task command; (b) a message levelinterface bus connecting each base module to said main system interfaceunit for providing a connected peripheral-controller in a base modulewith its own communication bus for message level data transfers withsaid main system; (c) a base module for each remote station forsupporting a plurality of peripheral-controllers at that station, saidbase module including:(c1) Distribution Control means for selectivelyconnecting an addressed peripheral-controller to said main system, forassigning local base priority signal codes to each peripheral-controllerand for assigning overall global-system priority signal codes to eachperipheral-controller; (c2) common backplane connection means forconnecting each peripheral-controller in a base module with common clockand common power supply and common maintenance-test means, and includingaddress lines for selectively connecting an addressedperipheral-controller to said Distribution Control means; (c3) interruptsignal means for requesting access to main memory from aperipheral-controller whose buffer memory is either full or empty andthus needs data transfer service from main memory; (c4) a plurality ofperipheral-controllers, each of which is dedicated via its owncommunication bus to a specific peripheral unit and wherein each of saidperipheral-controllers includes:(c4-1) processor logic means forexecution of I/O task command received from said main system; (c4-2)buffer memory storage means for storage of at least two full messagelength blocks of data, for storage of I/O task commands, Descriptor-Linkidentifier words and result-descriptor words; (c4-3) means to formulateresult-descriptor word signals to sense completion, incompletion orerror of an I/O task, said result-descriptor word signals beingsubsequently transmitted to said main system for initiation ofcorrective action; (c4-4) means to transfer message length blocks ofdata from the peripheral-controller to/from said main memory at thehighest transfer speed of main memory while transfers of data aresimultaneously occurring between other peripheral-controllers and theirperipheral terminals; (c4-5) status count means providing digital signalcounts to aid in controlling the sequential steps of communicationsbetween said peripheral-controller and to said main system systeminterface unit.
 2. The input-output system of claim 1, wherein said mainsystem interface unit includes:means providing separate channels forparallel data transfer between said main memory and said plurality ofperipheral-controllers, wherein each peripheral-controller is organizedto control data transfer operations between itself and a particularperipheral unit, the number of peripheral units and the number ofperipheral-controllers being determined by the number of parallel pathchannels provided in the main system interface unit.
 3. The input-outputsubsystem of claim 1, wherein each of said peripheral-controllersincludes:means for using a predetermined routine of communication andcontrol sequence steps, each step of which is numbered digitally andcommunicated by said peripheral-controller to said main system interfaceunit and to said processor logic means within saidperipheral-controller, to permit said peripheral-controller to signalits requirements and the status of its step sequences to said mainsystem interface unit.
 4. The input-output subsystem of claim 1, whereineach of said peripheral-controllers includes:status count generationmeans for generating a digital number signal representing each step of apredetermined communication discipline in order to signal said mainsystem interface unit with information which includes indicators:(i) ofthe clearance of buffer memory; (ii) that main system access is notneeded by the peripheral-controller; (iii) that the peripheral terminalunit connected to the peripheral-controller is not available for datatransfer; (iv) that the peripheral terminal unit connected to theperipheral-controller is now available for data transfer; (v) that thebuffer memory storage means is full and ready to transmit to the mainmemory; (vi) that the peripheral-controller requests connection to mainmemory; (vii) that the peripheral-controller requests a Descriptor-LinkWord to identify a particular data transfer task; (viii) that theperipheral-controller is transmitting result information to the mainsystem interface unit; (ix) that the peripheral-controller is acceptingdata from the main system; (x) that one character has been transmittedfrom the peripheral-controller to the main system; (xi) that theperipheral-controller can accept one more word from the main system;(xii) that the peripheral-controller has received and checked thelongitudinal parity of an I/O task command word; (xiii) that theperipheral-controller does not need any more data from the main system;(xiv) that the peripheral-controller has completed the data transfer ofone block of data to the main system and has another block to transfer;(xv) that the peripheral-controller has only one character to transfer;(xvi) that the peripheral-controller will transmit a result-descriptorword to signal the main system of the completion/incompletion of aspecial data transfer task that was initiated.
 5. The input-outputsubsystem of claim 1 wherein each of said base modules includes:meansfor establishing a local base priority code for eachperipheral-controller in a base module; means for establishing anoverall network global priority code for each peripheral-controller ineach base module; means for comparing the global priority codes in abase module of the peripheral-controllers concurrently requesting memoryaccess in order to select the highest priority codedperipheral-controller for connection to said main memory interface unit;and wherein said main memory interface unit includes:means to select,for main memory access, that peripheral-controller having the highestglobal priority code; and means to provide the highest priority for mainmemory accesses to the data transfer operations of the input-outputsubsystem thereby permitting main memory accesses by the main processoronly during unused memory cycles.